OMAP L138 EMAC receive problem

Andrew Setter

Other Parts Discussed in Thread: DP83848-EP, OMAP-L138, OMAPL138

Symptom: Ethernet 10 Base T operation fails to receive data approximately ~ 1 out of 10 transmissions. 100 Base Tx receives no data at all. Same operation in both half and full duplex regardless of auto negotiated or forced.

Board config: OMAP L138B-EP connected to a DP83848-EP PHY using RMII. Davinci-EMAC controlled using UBOOT and/or Linux 3.3 kernel with davinci-emac configuration leveraged from OMAP-L138 LCDK MCSDK software package but modified for use with this particular PHY and RMII. Identical symptoms with both UBOOT and Linux. The majority of testing is being performed with UBOOT.

Variables eliminated:

1) Signal integrity. The symptom would seem to point directly to this, so about the first week of debug as focused on signal integrity. Ethernet-level signal integrity has been verified with scope captures, adjustment of termination resistor location, an addition of bypass capacitors with varying levels of capacitance, and using a different set of known-good magnetics. Symptom persists with same character for both external and internal PHY loopbacks (that utilize the OMAP’s EMAC).

2) PHY configuration. PHY hardware configuration verified with correct netlist and board layout to OMAP (schematic excerpt included), rbias resistor and voltage correct, PFBOUT connections (to PFBIN 1 & 2) and capacitors correct, and strapping mode verified through register inspection. All PHY-only built-in-self-tests always pass, both internal and external loopback. PHY harmonic distortion testing passes, shows good quality. 50MHz PHY clock is oscillator generated and input into the PHY with excellent quality. The RMII_50MHz clock into the OMAP has excellent quality.

3) OMAP system configuration. Pinmuxes are set correctly, and system level clocks and PLL registers are set correctly and legally (multiple ranges of speeds were tried). No known issues with RAM or Flash operations.

4) EMAC configuration. EMAC configuration verified by comparison with working network operation on the OMAP L138 LCDK dev kit, but with modifications only for RMII operation and configuration for the DP83848 PHY. Networking logic and procedures are verified to be correct according to the L138 and DP83848 datasheets, as well as known working with the dev kit. Due to the fact that the LCDK dev kit uses MII, and works just fine for 10 and 100 base T, heavy scrutiny was given to our RMII configuration to ensure we were configuring it correctly. Speed/Duplex/Autonegotiation configuration is verified in both the PHY and EMAC through register inspection, debug statements, and hardware scoping.

Where we are:

The attached UBOOT terminal output with debug statements shows dumps from both the EMAC statistics registers and select PHY registers during a successful communication sequence and a subsequent failed communication sequence.

The communication sequence operates as follows:

1) A ping UBOOT command is issued

2) EMAC device is opened, which initializes the EMAC and sets up the descriptor pointers. A statistics register block dump is performed to show clean all zeros.

3) ARP request begins and a broadcast data packet is sent out.

4) Laptop responds with ARP reply and is received. During a receive, the EMAC statistics registers and PHY registers are dumped.

5) An ICMP echo request packet is sent out.

6) An ICMP echo reply is received and the statistics and PHY registers are again dumped.

4544.8865.ForTiEmail.txt

Flash: 32 MiB
MMC:   davinci: 0
In:    serial
Out:   serial
Err:   serial
Net:   PHY_DP83848 phy num: 0
Eth init done - ready for autonegotiation
num_phy: 1
Eth init done - in conditional
Entered DP83848 is phy connected - phy_addr: 1.
Between 1 and 2 - id1: 2000.
--> id1 : 0x2000--> DP83848_PHYID1_OUI : 0x2000--> id2 : 0x5c90--> DP83848_PHYID2_OUI : 0x5c90Eth init done - begin autonegotiation [0]
Entering dp83848_auto_negotiate.
dp83848_auto_negotiate - past control reg read.
-->Starting Autonegotiation!
-->Autonegotiation PASSED!
&emac->MACCONTROL register before: 0000
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0000
dp83848_get_link_speed exiting...
Autoneg return: 1&emac->MACCONTROL register before: 0000
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0000
dp83848_get_link_speed exiting...
Init return: 1Eth init done - autonegotiation should be done
DaVinci-EMAC
Pinmux[0] @ 0x01c14120: 0x44080000
Pinmux[1] @ 0x01c14124: 0x00000000
Pinmux[2] @ 0x01c14128: 0x88888880
Pinmux[3] @ 0x01c1412c: 0x88888888
Pinmux[4] @ 0x01c14130: 0x00222288
Pinmux[5] @ 0x01c14134: 0x11000000
Pinmux[6] @ 0x01c14138: 0x00000000
Pinmux[7] @ 0x01c1413c: 0x00110001
Pinmux[8] @ 0x01c14140: 0x11111111
Pinmux[9] @ 0x01c14144: 0x11111111
Pinmux[10] @ 0x01c14148: 0x11222222
Pinmux[11] @ 0x01c1414c: 0x11111111
Pinmux[12] @ 0x01c14150: 0x11111111
Pinmux[13] @ 0x01c14154: 0x00000000
Pinmux[14] @ 0x01c14158: 0x88888800
Pinmux[15] @ 0x01c1415c: 0x00000080
Pinmux[16] @ 0x01c14160: 0x00000000
PllRegs[0] @ 0x01c11110: 0x00000018
PllRegs[1] @ 0x01c11114: 0x00008000
PllRegs[2] @ 0x01c11118: 0x00008000
PllRegs[3] @ 0x01c1111c: 0x00008001
PllRegs[4] @ 0x01c11120: 0x00008004
PllRegs[5] @ 0x01c11124: 0x00008000
PllRegs[6] @ 0x01c11128: 0x00008001
PllRegs[7] @ 0x01c1112c: 0x00000000
PllRegs[8] @ 0x01c11130: 0x00000000
PllRegs[9] @ 0x01c11134: 0x00000000
PllRegs[10] @ 0x01c11138: 0x00000001
PllRegs[11] @ 0x01c1113c: 0x00000006
PllRegs[12] @ 0x01c11140: 0x000001ff
PllRegs[13] @ 0x01c11144: 0x00000000
PllRegs[14] @ 0x01c11148: 0x00000003
PllRegs[15] @ 0x01c1114c: 0x00000003
PllRegs[16] @ 0x01c11150: 0x000001ff
PllRegs[17] @ 0x01c11154: 0x00000000
PllRegs[18] @ 0x01c11158: 0x00000000
PllRegs[19] @ 0x01c1115c: 0x00000000
PllRegs[20] @ 0x01c11160: 0x00008003
PllRegs[21] @ 0x01c11164: 0x00008002
PllRegs[22] @ 0x01c11168: 0x00008000
PllRegs[23] @ 0x01c1116c: 0x00008005
PllRegs[24] @ 0x01c11170: 0x00008005
Hit any key to stop autoboot:  0


U-Boot > ping 192.168.1.95
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000000 0x00000000 0x00000000 0x00000000
WE DID IT!
&emac->MACCONTROL register before: 8021
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Using DaVinci-EMAC device

============STARTING PING=============
sending ARP for 5f01a8c0
ARP broadcast 1
&emac->MACCONTROL register before: 0020
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0xc000003c
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000001 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000040 0x00000001 0x00000001 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000040 0x00000002 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000080 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
Got ARP
&emac->MACCONTROL register before: 0020
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Rx Header Desc Pointer: 0x01e20010
emac_rx_active_head: 0x01e20010
emac_rx_active_head->pkt_flag_len: 0xc000003c
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000002 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000080 0x00000002 0x00000001 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000080 0x00000004 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000100 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
Got ICMP ECHO REPLY, return 42 bytes
host 192.168.1.95 is alive


U-Boot > ping 192.168.1.95
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000000 0x00000000 0x00000000 0x00000000
WE DID IT!
&emac->MACCONTROL register before: 8021
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Using DaVinci-EMAC device

============STARTING PING=============
sending ARP for 5f01a8c0
ARP broadcast 1
&emac->MACCONTROL register before: 0020
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000001 0x00000001 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000040 0x00000001 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000081 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000001 0x00000001 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000040 0x00000001 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000081 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
ARP broadcast 2
&emac->MACCONTROL register before: 0020
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000002 0x00000002 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000080 0x00000002 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000102 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000002 0x00000002 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000080 0x00000002 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000102 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
ARP broadcast 3
&emac->MACCONTROL register before: 0020
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000003 0x00000003 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x000000c0 0x00000003 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000182 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000003 0x00000003 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x000000c0 0x00000003 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000182 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
ARP broadcast 4
&emac->MACCONTROL register before: 0020
Set EMAC to Duplex Half Enabled!
Set EMAC to Speed 10!
&emac->MACCONTROL register after: 0020
dp83848_get_link_speed exiting...
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000004 0x00000004 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000100 0x00000004 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000202 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011
Rx Header Desc Pointer: 0x01e20000
emac_rx_active_head: 0x01e20000
emac_rx_active_head->pkt_flag_len: 0x20000000
(emac_rx_active_head+1)->pkt_flag_len: 0x20000000
(emac_rx_active_head+2)->pkt_flag_len: 0x20000000
      StatRegs       BaseAddr   0x00000000 0x00000004 0x00000008 0x0000000c
|------------------|-----------|----------|----------|----------|----------|
  StatReg[00..04] @ 0x01e23200: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[04..08] @ 0x01e23210: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[08..12] @ 0x01e23220: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[12..16] @ 0x01e23230: 0x00000000 0x00000004 0x00000004 0x00000000
  StatReg[16..20] @ 0x01e23240: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[20..24] @ 0x01e23250: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[24..28] @ 0x01e23260: 0x00000000 0x00000100 0x00000004 0x00000000
  StatReg[28..32] @ 0x01e23270: 0x00000000 0x00000000 0x00000000 0x00000000
  StatReg[32..36] @ 0x01e23280: 0x00000202 0x00000000 0x00000000 0x00000000
  DP83848_PHY_STAT_REG (0x10): 4113
  DP83848_FALSE_SNS_CNTR_REG (0x14): 0000
  DP83848_RX_ERROR_CNTR_REG (0x15): 0000
  DP83848_ENG_DTCT_CTRL_REG (0x1d): 6011

Abort
ping failed; host 192.168.1.95 is not alive
U-Boot >

Items to note about a successful communication sequence: After the first ARP request transmit and ARP reply receive, tThe value of the EMAC register, RXOCTECTS (0x01e23230), shows 0x40 bytes of good data received, the value of the EMAC register, TXOCTECTS (0x01e23264), shows 0x40 bytes of good data transmitted, and the value of NETOCTETS (0x01e23280) shows a total of 0x80 bytes RX and TX data.

Items to note about a failed communication sequence: After the first ARP request transmit, there is NO RECEIVE of the ARP reply, even though we see it being sent with wireshark on the communicating laptop. The packet receive function gets stuck in a loop because the RX descriptor data never releases from its initial configuration. The value of the EMAC register, TXOCTECTS (0x01e23264), shows 0x40 bytes of good data transmitted, the value of RXOCTECTS shows ZERO bytes transmitted, but the value of NETOCTETS (0x01e23280) shows a total of 0x81 bytes RX and TX data. This implies the data was physically received by the PHY, transmitted to the EMAC over RMII, but for some reason not presented into the receive descriptor memory. A description of the NETOCTETS register implies this is due to the data being transmitted before a carrier-loss was experienced. But when we probe the CRS_DV signal on both successful and failed 10 Base T receives, we see the same one-toggle of the CRS_DV (indicating carrier sense was de-asserted). At the end of every failed (they all fail) 100 Base TX receives, we see 3 toggles of the CRS_DV signal (see scope trace). Because we see this every time, we don’t understand why sometimes RXOCTECTS is zero, and sometimes it is full.

Channel 1 (yellow) CRS_DV (at end of RMII packet)

Channel 3 (purple) RxD[0]

This implied that there might be a problem with us losing the carrier signal, and we are aware that we are not isolating the PHY’s analog power section using a ferrite bead and additional decoupling. We tried adding quite a bit of extra decoupling on our board 3x 0.22uF, 10uF and 100uF right next to the PHY’s analog section to hopefully quite it down enough, but we saw no effect on the character of the failures. It’s still not out of the question that properly isolating the quiet section would fix it, but it is very difficult for us to prove at this time without a board re-spin.

Therefore, any other thoughts on why data is not getting received?

over 9 years ago

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

Hi Andrew,

Have you configured CFGCHIP3 register (0x01c14188 -> 8th bit) for RMII mode ?

OMAPL138 SDI EVM board configured RMII by default in u-boot and linux source code.

From s/w side, You can refer to the source code of u-boot as well linux.

mcsdk_1_01_00_02/board-support/u-boot-2012.04.01-psp03.22.00.06.sdk/include/configs/da850sdi.h

#define CONFIG_DRIVER_TI_EMAC_USE_RMII

board/davinci/da8xxevm/da850sdi.c

void davinci_emac_mii_mode_sel(int mode_sel)

arch/arm/cpu/arm926ejs/davinci/misc.c

/*
 * Set the mii mode as MII or RMII
 */
#if defined(CONFIG_SOC_DA8XX)
void davinci_emac_mii_mode_sel(int mode_sel)
{
	int val;

	val = readl(&davinci_syscfg_regs->cfgchip3);
	if (mode_sel == 0)
		val &= ~(1 << 8);
	else
		val |= (1 << 8);
	writel(val, &davinci_syscfg_regs->cfgchip3);
}
#endif

mcsdk_1_01_00_02/board-support/linux-3.3-psp03.22.00.06.sdk/arch/arm/mach-davinci/board-da850-sdi.c

"CONFIG_DA850_SDI_MII" is not declared in board file.

	val = __raw_readl(cfg_chip3_base);

#ifndef CONFIG_DA850_SDI_MII
	soc_info->emac_pdata->rmii_en = 1;
	rmii_en = 1;
#endif

	if (rmii_en) {
		val |= BIT(8);
		ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
		pr_info("EMAC: RMII PHY configured, MII PHY will not be"
							" functional\n");
	} else {
		val &= ~BIT(8);
		ret = davinci_cfg_reg_list(da850_evm_mii_pins);
		pr_info("EMAC: MII PHY configured, RMII PHY will not be"
							" functional\n");
	}

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Hello Andrew,

I have some doubt and recommendation on your design.

1. Why 100 ohm series resistors on RX and TX lines ? Are these resistors provided based on SI analysis ?

2. It is recommended to isolate the PHY analog power from digital power using ferrite bead.

3. It is recommended to pull down the unsed TX lines in PHY.

You can refer the below application note specific to DP83848 RMII mode that explains the CRS_DV generation during read. You can also ensure the configuration settings as explained in the app note.

http://www.ti.com/lit/an/snla076a/snla076a.pdf

Regards,

Senthil

0 Andrew Setter over 9 years ago in reply to Titusrathinaraj Stalin

Prodigy 40 points

Hi Titus,

Thanks for getting back so quickly. The CFGCHIP3 register was one of the first things we checked. I can confirm it is being correctly configured. This is verified by the fact that we can transmit data using RMII just fine. All of the other configuration items pointed out in your quoted code are also configured by our software.

0 Andrew Setter over 9 years ago in reply to Senthilkumar Srinivasan

Prodigy 40 points

Hi Senthil,

To address your concerns:

1) The 100 ohm resistors weren't the result of an analysis, but just as a general source termination preference. The signal integrity at pins of the OMAP is quite good. The PHY isn't more than ~1.5 inches away from the OMAP on our board.

2) This is something we know we didn't do perfectly. We think this could be a good be a source of the problem, but we're having a hard time verifying it without doing a board respin. We tried adding an array of decoupling directly on top of the 3V3 analog supply pin, but it didn't have any effect. It could very well be just not good enough as having it isolated with a ferrite bead.

3) This is something we weren't aware of and we can try adding some pull downs, although we have seem to have no problem transmitting at either speed using RMII.

We are very familiar with that app note and I can confirm we are configuring all of those registers in the PHY. This is verified by the fact that the PHY is transmitting data just fine using RMII. The PHY seems to be receiving ethernet data and transmitting it out on RMII. We're seeing the toggling of the CRS_DV line at the end of RMII receive packets (as described in the app note to indicate losing carrier sense) , but we always see the toggling, even during successful 10 base T receives. The scope trace I posted above is what the toggling looks like at the end of a 100 base Tx receives.

0 Andrew Setter over 9 years ago in reply to Andrew Setter

Prodigy 40 points

Does anyone have any other ideas?

0 Senthilkumar Srinivasan over 9 years ago in reply to Andrew Setter

TI__Mastermind 43660 points

Hello Andrew,

Sorry for the delayed response. I believe the problem is related to Ethernet PHY side. So we are moving this thread to Ethernet forum for better support.

Regards,

Senthil

0 Patrick OFarrell over 9 years ago in reply to Senthilkumar Srinivasan

TI__Mastermind 31600 points

Andrew,

Could you confirm the source of the 50MH reference clock to the MAC? It is difficult to tell based on the partial schematic provided, but I suspect this is provided by the 25MHz_OUT pin from the DP83848.

If that is the case, I think the issue may be timing on the RMII connections to the MAC. To check this, you could rerun your test after depopulating the series resistor on the 25MHz_OUT trace and wiring in the oscillator output as the 50MHz reference clock to the MAC.

Patrick

0 Luke Thomas over 9 years ago in reply to Patrick OFarrell

Prodigy 10 points

Patrick,

It looks like you nailed it. We will do more checks next week, but it has been working beautifully since we made the rework you suggested.

Thanks!

Luke

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OMAP L138 EMAC receive problem