Problem debugging a program in CCS (OMAPL138 expermineter kit)

What example are you debugging ?
Is that your own code or TI provided ?
Have you tried "step into" debugging (F5) on the code ?

Hello,

It is my own code that I'm debugging. I've also tried "step into" debugging.

Here is my code:

#include <math.h>
#include "L138_bios_aic3106_init.h"


float freq_par=0.0f;
float y0=0.0f;
float y1=1.0f;
float y2=0.0f;

const double pi = 3.1415926f;


void interrupt4(void) // interrupt service routine
{
int left_sample;

// IIR with poles on unit circle
y0 = freq_par * y1 - y2;
y2 = y1;
y1 = y0;

left_sample = (int)(y0*4000);
output_sample(left_sample);

return;
}

int main(void)
{
float frel=0.02f; //corresponds to approx 1kHz at fs=48kHz

freq_par=2*cos(2*pi*frel);

L138_bios_initialise_intr(FS_48000_HZ,ADC_GAIN_0DB,DAC_ATTEN_0DB);
}


The L138_bios_aic3106_init.c file is the following:


// L138_bios_aic3106_init.c
//

#include "L138_bios_aic3106_init.h"

AIC31_data_type AIC31_data;

typedef struct BITVAL // used in function prbs()
{
unsigned int b0:1, b1:1, b2:1, b3:1, b4:1, b5:1, b6:1;
unsigned int b7:1, b8:1, b9:1, b10:1, b11:1, b12:1,b13:1;
unsigned int dweebie:2; //Fills the 2 bit hole - bits 14-15
} bitval;

typedef union SHIFT_REG
{
unsigned int regval;
bitval bt;
} shift_reg;
int fb = 1; // feedback variable
shift_reg sreg = {0xFFFF}; // shift register

uint32_t prand_seed = 1; // used in function prand()

void output_sample(int32_t out_data)
{
AIC31_data.uint = out_data;
if (poll) while (!CHKBIT(MCASP->SRCTL11, XRDY));
MCASP->XBUF11 = AIC31_data.uint;
}

void output_left_sample(int16_t out_data)
{
AIC31_data.uint = 0;
AIC31_data.channel[LEFT]=out_data;
if (poll) while (!CHKBIT(MCASP->SRCTL11, XRDY));
MCASP->XBUF11 = AIC31_data.uint;
}

void output_right_sample(int16_t out_data)
{
AIC31_data.uint = 0;
AIC31_data.channel[RIGHT]=out_data;
if (poll) while (!CHKBIT(MCASP->SRCTL11, XRDY));
MCASP->XBUF11 = AIC31_data.uint;
}

int32_t input_sample(void)
{
if (poll) while (!CHKBIT(MCASP->SRCTL12, RRDY));
AIC31_data.uint = MCASP->XBUF12;
return (AIC31_data.uint);
}

int16_t input_left_sample(void)
{
if (poll) while (!CHKBIT(MCASP->SRCTL12, RRDY));
AIC31_data.uint = MCASP->XBUF12;
return (AIC31_data.channel[LEFT]);
}

int16_t input_right_sample(void)
{
if (poll) while (!CHKBIT(MCASP->SRCTL12, RRDY));
AIC31_data.uint = MCASP->XBUF12;
return (AIC31_data.channel[RIGHT]);
}

// configure and initialise McASP0 for interrupt-based i/o

void L138_bios_init_mcasp_intr()
{

// globally reset McASP0
MCASP->GBLCTL = 0;

// configure McASP0 receive registers
MCASP->RMASK = 0xFFFFFFFF;
MCASP->RFMT = 0x000080F8;
MCASP->AFSRCTL = 0x00000000;
MCASP->ACLKRCTL = 0x00000000;
MCASP->AHCLKRCTL = 0x00000000;
MCASP->RTDM = 0x00000001; // TDM timeslot 0
MCASP->RINTCTL = 0x00000000;
MCASP->RCLKCHK = 0x00000000;

// configure McASP0 transmit registers
MCASP->XMASK = 0xFFFFFFFF;
MCASP->XFMT = 0x000080F8;
MCASP->AFSXCTL = 0x00000000;
MCASP->ACLKXCTL = 0x00000000;
MCASP->AHCLKXCTL = 0x00000000;
MCASP->XTDM = 0x00000001; // TDM timeslot 0
MCASP->XINTCTL = 0x00000020; // interrupt on transmit
MCASP->XCLKCHK = 0x00000000;
// configure serialisers (11 for xmit, 12 for rcv)
MCASP->SRCTL11 = 0x000D;
MCASP->SRCTL12 = 0x000E;

// config pin function and direction.
MCASP->PFUNC = 0;
MCASP->PDIR = 0x00000800;

//
MCASP->DITCTL = 0x00000000;
MCASP->DLBCTL = 0x00000000;
MCASP->AMUTE = 0x00000000;


// enable the audio clocks, verifying each bit is properly set.
SETBIT(MCASP->XGBLCTL, XHCLKRST);
while (!CHKBIT(MCASP->XGBLCTL, XHCLKRST)) {}
SETBIT(MCASP->RGBLCTL, RHCLKRST);
while (!CHKBIT(MCASP->RGBLCTL, RHCLKRST)) {}

MCASP->XSTAT = 0x0000FFFF; // Clear all
MCASP->RSTAT = 0x0000FFFF; // Clear all


SETBIT(MCASP->XGBLCTL, XSRCLR);
while (!CHKBIT(MCASP->XGBLCTL, XSRCLR)) {}
SETBIT(MCASP->RGBLCTL, RSRCLR);
while (!CHKBIT(MCASP->RGBLCTL, RSRCLR)) {}

// Write zero to serialiser buffers so that no underrun occurs after releasing the state machine
MCASP->XBUF11 = 0;
MCASP->RBUF12 = 0;

SETBIT(MCASP->XGBLCTL, XSMRST);
while (!CHKBIT(MCASP->XGBLCTL, XSMRST)) {}
SETBIT(MCASP->RGBLCTL, RSMRST);
while (!CHKBIT(MCASP->RGBLCTL, RSMRST)) {}

SETBIT(MCASP->XGBLCTL, XFRST);
while (!CHKBIT(MCASP->XGBLCTL, XFRST)) {}
SETBIT(MCASP->RGBLCTL, RFRST);
while (!CHKBIT(MCASP->RGBLCTL, RFRST)) {}

// wait for transmit ready and send a dummy byte
while(!CHKBIT(MCASP->SRCTL11, XRDY)) {}
MCASP->XBUF11 = 0;

}



// initialise AIC3106 codec by writing to its control registers
// sampling frequency, ADC gain, and DAC attenuation are set according to parameters passed


void L138_init_aic3106_registers(int32_t fs, int16_t adc_gain, int16_t dac_atten)
{
// not every register is set here - some are left with default(reset) values
// each AIC3106 register is 8 bits wide

AIC3106_writeRegister( 0, 0x00 ); // AIC3106_PAGESELECT is PAGE 0 REG 0
AIC3106_writeRegister( 1, 0x80 ); // reset AIC3106 using REG 1

switch(fs) // set up sampling rate - default 8kHz
{
case FS_8000_HZ:
AIC3106_writeRegister( 2, 0xAA );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_9600_HZ:
AIC3106_writeRegister( 2, 0x88 );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_11025_HZ:
AIC3106_writeRegister( 2, 0x66 );
AIC3106_writeRegister( 7, 0x8A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_12000_HZ:
AIC3106_writeRegister( 2, 0x66 );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_16000_HZ:
AIC3106_writeRegister( 2, 0x44 );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_19200_HZ:
AIC3106_writeRegister( 2, 0x33 );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_22050_HZ:
AIC3106_writeRegister( 2, 0x22 );
AIC3106_writeRegister( 7, 0x8A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_24000_HZ:
AIC3106_writeRegister( 2, 0x22 );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_32000_HZ:
AIC3106_writeRegister( 2, 0x11 );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_44100_HZ:
AIC3106_writeRegister( 2, 0x00 );
AIC3106_writeRegister( 7, 0x8A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_48000_HZ:
AIC3106_writeRegister( 2, 0x00 );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
default:
AIC3106_writeRegister( 2, 0xAA );
AIC3106_writeRegister( 7, 0x0A ); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
}

AIC3106_writeRegister( 3, 0x22 ); // disable PLL and set Q=4(relevant) and P=2(irrelevant)
// fsref will be MCLK/(128*Q) = 48000
// MCLK on eXperimenter is 24.576MHz from on-board Citizen oscillator
AIC3106_writeRegister( 4, 0x20 ); // J=8 (irrelevant since PLL disabled)
AIC3106_writeRegister( 5, 0x6E ); // D=7075 MS bits (irrelevant since PLL disabled)
AIC3106_writeRegister( 6, 0x23 ); // D=7075 LS bits (irrelevant since PLL disabled)
AIC3106_writeRegister( 8, 0xC0 ); // Audio Interface Control A BCLK=Slave(input), WCLK=Slave(input)
AIC3106_writeRegister( 9, 0x40 ); // Audio Interface Control B DSP mode (1 slot), 32 bit slot width

AIC3106_writeRegister( 12, 0x00 ); // Audio Interface Control C Data offset=0


AIC3106_writeRegister( 10, 0x00 ); // Audio Interface Control C Data offset=0
// WARNING - this assumes that adc_gain is a sensible value
AIC3106_writeRegister( 15, adc_gain ); // Left ADC Programmable Gain Amplifier Mute=OFF Gain=0dB
AIC3106_writeRegister( 16, adc_gain ); // Right ADC Programmable Gain Amplifier Mute=OFF Gain=0dB
AIC3106_writeRegister( 19, 0x04 ); // power up ADCs
AIC3106_writeRegister( 22, 0x04 );
AIC3106_writeRegister( 37, 0xE0 ); // DAC Power & Output Dvr LeftDAC=ON, RightDAC=ON, HPLCOM=SingleEnd]
// WARNING - this assumes that dac_atten is a sensible value
AIC3106_writeRegister( 43, dac_atten ); // Left DAC Digital Volume Mute=OFF, Gain=0dB
AIC3106_writeRegister( 44, dac_atten ); // Right DAC Digital Volume Mute=OFF, Gain=0dB
AIC3106_writeRegister( 82, 0x80 ); // was 0x80 DAC_L1 to LEFT_LOP/M Volume Routed, Gain=0dB
AIC3106_writeRegister( 86, 0x09 ); // LEFT_LOP/M Output Mute=OFF bit3 bit0 is REad only ?! must be set!
AIC3106_writeRegister( 92, 0x80 ); // was 0x80 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed]
AIC3106_writeRegister( 93, 0x09 ); // 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON]
AIC3106_writeRegister( 101, 0x01 ); // 101 GPIO Control Register B <- [CODEC_CLKIN = CLKDIV_OUT]
AIC3106_writeRegister( 102, 0 );

}


// initialisation routine called by example program for interrupt-based i/o

void L138_bios_initialise_intr(int32_t fs, int16_t adc_gain, int16_t dac_atten)
{

poll = 0; // used in input_sample() and output_sample() functions

EVMOMAPL138_init();
EVMOMAPL138_initRAM();
USTIMER_init();


EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_MCASP0, PSC_ENABLE);
EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_0, PINMUX_MCASP_MASK_0, PINMUX_MCASP_VAL_0);
EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_1, PINMUX_MCASP_MASK_1, PINMUX_MCASP_VAL_1);

*( volatile uint32_t* )(0x01C22024) = 0;
*( volatile uint32_t* )(0x01C22030) = 2;
*( volatile uint32_t* )(0x01C2200C) = 5;
*( volatile uint32_t* )(0x01C22010) = 5;
*( volatile uint32_t* )(0x01C22024) |= 0x20;


CSR = 0x0000; // disable interrupts globally while initialising
// GIE is bit 0 of CSR register (CSR is special CCS
// C compiler type cregister and given value in c6x.h)

L138_init_aic3106_registers(fs, adc_gain, dac_atten);

L138_bios_init_mcasp_intr();

// clear all pending interrupt flags
// interrupt clear register ICR is used to clear bits in interrupt flag register IFR
ICR = 0xFFF0; // ICR bits 3, 2, 1, and 0 are reserved, read as 0, write has no effect
IER |= 0x10; //enable INT4 (bit 4)
}

int prbs(void) // generate pseudo-random sequence
{
int prnseq;
if(sreg.bt.b0)
prnseq = -NOISELEVEL; //scaled negative noise level
else
prnseq = NOISELEVEL; //scaled positive noise level
fb =(sreg.bt.b0)^(sreg.bt.b1); //XOR bits 0,1
fb^=(sreg.bt.b11)^(sreg.bt.b13); //with bits 11,13 -> fb
sreg.regval<<=1;
sreg.bt.b0=fb; //close feedback path
return prnseq; //return noise sequence value
}



uint32_t rand31_next()
{
uint32_t hi, lo;

lo = 16807 * (prand_seed & 0xFFFF);
hi = 16807 * (prand_seed >> 16);

lo += (hi & 0x7FFF) << 16;
lo += hi >> 15;

if (lo > 0x7FFFFFFF) lo -= 0x7FFFFFFF;

return(prand_seed = (uint32_t)lo);
}

int16_t prand()
{
return ((int16_t)(rand31_next()>>18)-4096);
}


The L138_bios_aic3106_int.h file is the following:


// L138_bios_aic3106_int.h
//

#include "stdio.h"
#include "stdlib.h"
#include "types.h"
#include "evmomapl138.h"
#include "evmomapl138_timer.h"
#include "evmomapl138_gpio.h"
#include "evmomapl138_i2c.h"
#include "evmomapl138_mcasp.h"
#include "evmomapl138_aic3106.h"

#define FS_8000_HZ 8000
#define FS_9600_HZ 9600
#define FS_11025_HZ 11025
#define FS_12000_HZ 12000
#define FS_16000_HZ 16000
#define FS_19200_HZ 19200
#define FS_22050_HZ 22050
#define FS_24000_HZ 24000
#define FS_32000_HZ 32000
#define FS_44100_HZ 44100
#define FS_48000_HZ 48000

#define ADC_GAIN_0DB 0
#define ADC_GAIN_3DB 6
#define ADC_GAIN_6DB 12
#define ADC_GAIN_9DB 18
#define ADC_GAIN_12DB 24
#define ADC_GAIN_15DB 30
#define ADC_GAIN_18DB 36
#define ADC_GAIN_21DB 42
#define ADC_GAIN_24DB 48
#define ADC_GAIN_27DB 54
#define ADC_GAIN_30DB 60
#define ADC_GAIN_33DB 66
#define ADC_GAIN_36DB 72
#define ADC_GAIN_39DB 78
#define ADC_GAIN_42DB 84
#define ADC_GAIN_45DB 90
#define ADC_GAIN_48DB 96
#define ADC_GAIN_51DB 102

#define DAC_ATTEN_0DB 0
#define DAC_ATTEN_3DB 6
#define DAC_ATTEN_6DB 12
#define DAC_ATTEN_9DB 18
#define DAC_ATTEN_12DB 24
#define DAC_ATTEN_15DB 30
#define DAC_ATTEN_18DB 36
#define DAC_ATTEN_21DB 42
#define DAC_ATTEN_24DB 48

#define EDMA_3CC_IECRH *( unsigned int* )( 0x01c0105c )
#define EDMA_3CC_EECRH *( unsigned int* )( 0x01c0102c )
#define EDMA_3CC_ICRH *( unsigned int* )( 0x01c01074 )
#define EDMA_3CC_ECRH *( unsigned int* )( 0x01c0100c )

#define EDMA_3CC_IECR *( unsigned int* )( 0x01c01058 )
#define EDMA_3CC_EECR *( unsigned int* )( 0x01c01028 )
#define EDMA_3CC_EESR *( unsigned int* )( 0x01c01030 )
#define EDMA_3CC_ICR *( unsigned int* )( 0x01c01070 )
#define EDMA_3CC_IPR *( unsigned int* )( 0x01c01068 )
#define EDMA_3CC_ECR *( unsigned int* )( 0x01c01008 )
#define EDMA3_IESR *( unsigned int* )( 0x01c01060 )
#define EDMA3_DRAE1 *( unsigned int* )( 0x01c00348 )
#define INTC_INTMUX1 *( unsigned int* )( 0x01800104 )
#define EVTCLR0 *( unsigned int* )( 0x01080040 )
#define EVTCLR1 *( unsigned int* )( 0x01080044 )

// pinmux defines.
#define PINMUX_MCASP_REG_0 (0)
#define PINMUX_MCASP_MASK_0 (0x00FFFFFF)
#define PINMUX_MCASP_VAL_0 (0x00111111)
#define PINMUX_MCASP_REG_1 (1)
#define PINMUX_MCASP_MASK_1 (0x000FF000)
#define PINMUX_MCASP_VAL_1 (0x00011000)

#define LEFT 0
#define RIGHT 1

static int poll;

void L138_bios_initialise_edma(int32_t fs, int16_t adc_gain, int16_t dac_atten);
void L138_bios_initialise_poll(int32_t fs, int16_t adc_gain, int16_t dac_atten);
void L138_bios_initialise_intr(int32_t fs, int16_t adc_gain, int16_t dac_atten);

int32_t input_sample(void);
int16_t input_right_sample(void);
int16_t input_left_sample(void);
void output_sample(int32_t out_data);
void output_right_sample(int16_t out_data);
void output_left_sample(int16_t out_data);
int16_t prand();
int prbs();

typedef union
{
uint32_t uint;
short channel[2];
} AIC31_data_type;


extern cregister volatile unsigned int CSR; // control status register
extern cregister volatile unsigned int ICR; // interrupt clear register
extern cregister volatile unsigned int IER; // interrupt enable register
extern cregister volatile unsigned int ISTP; // interrupt

Hello,

thanks a lot for your help.

Regards,

Laura