OMAPL138-EP Memory Map

Please refer to the page no 25 of OMAPL138-EP data sheet.

www.ti.com/lit/ds/symlink/omapl138b-ep.pdf

You can interface 32MB memory for each chip select of EMIF.

Edited:
And also you can interface totally 512MB RAM on DDR2 interface.

Apologize, I will come back regarding DDR2 interface.

Thanks.  Is the 32MB limit also true for NAND connected to the CS3?  The LCDK reference design from TI uses 4Gbit NAND flash.  Also, figure 5-11 on datasheet shows 16Gbit NAND connected to OMAP.  What is the max limit on NAND.  The memory map needs to be corrected for SDRAM, DDR2 and NAND.

NAND memory addressing doesn't use the address lines so there isn't a limit to the size of NAND part that can be used to interface with EMIF16 (it is not limited by the memory mapped 32MB like NOR etc, which use address lines). The addressing is handled by the software driver that you develop. 

If you are using NAND for booting, you might find the following wikis useful

Mukul,

I don't fully follow your response.  NAND uses EMA Data pin to provide both address and data.  How does OMAP CPU know how to address the NAND.  The NAND controller should still be mapped to some OMAP CPU address.  I am using NAND to not only boot the OMAP, but to also store data which OMAP CPU will access later.

Regards,

Amit

There seems to be some disconnect here.  I am not asking how the NAND flash works.  I understand how the address and data are multiplexed on the pins and the commands are sent serially.  The question is how does the NAND address map to OMAPL138's address space?  I don't fully understand that.  From the memory map, 0x6200 0000 to 0x63FF FFFF are allocated to Chip Select 3 (NAND Flash).  This is only 32MB of address space.  This should be regardless of whether the Flash device connected is serial or parallel.  This means when OMAPL138 want to access beyond 0x63FF FFFF (32MB) of Flash address, it has to use another chip select?  If not, accesses beyond 0x63FF FFFF will fall in other areas including CS4, CS5, EMIFA control regs,... (see memory map).

Another side question, I will have two devices connected on EMIFA bus - NAND Flash (CS3) and FPGA (CS2).  Will OMAP EMIFA bus be able to handle two loads or I need buffers?

Amit,

Any type of asynchronous memory can be connected to EMA_CS [5:2]. (NOR, SRAM and NAND), your assumption is correct with respects to NOR and SRAM memories which use the address and data bus to access every location (random access supported) in that case 32MB address spaces is limited to every chip select .

NAND flash doesn’t depends upon the external address & data bus to access every location (no-random access) the data must be read/write on a block-wise basis (also known as page access) using commands which is send through bidirectional data bus . So, the 32MB chips select address space is mainly used for accessing the NAND flash on-chip registers  resources not for reading the entire data which is stored in the memory (say for example 1Gb). Please see the NAND device datasheet for memory mapping and address details that have the start and end address for the entire capacity for x8 or x16 interfaces.

Epilogue

NAND flash are available in different capacities and comparatively huge in size mainly used for storage, imagine how can we memory map that much huge space in the SoC’s that too for various capacities?

CPU can’t see this memory as direct memory mapped like NOR or SRAM which uses dedicated address and data pins to access data. NAND Flash devices do not contain dedicated address pins .The bidirectional I/O pins transfer address, data, and instruction information.

CPU can send commands to NAND flash to read /write the data from the memory block’s and the data can be send to an DDR memory space, LCD display, Ethernet or other process which the application intended to use. So, the NAND device doesn’t depends upon the chip select address space 32MB.

EMIF DC loading

EMIFA supports up to 100 MHz for two asynchronous memory loads as per datasheet, but you can cross check the I/O sink current requirement for both the device (NAND and FPGA) to make sure you met the margin.

Additional loads will limit the operation to lower speeds and the maximum speed should be Confirmed by board simulation using IBIS models.

Regards

Antony

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