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Jtag connectivity problems Omap L138 custom board

Other Parts Discussed in Thread: OMAPL138

Hello,

I have a custom board with LogicPD Omap L138 SOM.

This is the second revision of the board, the first one worked great.

I am trying to connect the JTAG (XDS100V2) to the MCU,

All the lines are connected correctly.

When trying to connect with adaptive clocking (1Mhz) I get the following error:

ICEPICK_C: Error connecting to the target: (Error -150 @ 0x0) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 5.1.641.0) 

When Testing the connection, I get:

[Start: Texas Instruments XDS100v2 USB Emulator]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\Yoel\AppData\Local\TEXASI~1\CCS\
TI\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Feb 18 2015'.
The library build time was '23:56:50'.
The library package version is '5.1.641.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The JTAG IR instruction path-length was not recorded.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-154' (0xffffff66).
The title is 'SC_ERR_FTDI_WRITE'.

The explanation is:
One of the FTDI driver functions used to
write data returned bad status or an error.

[End: Texas Instruments XDS100v2 USB Emulator]

 

When I change it to Fixed 1Mhz freq, I can connect to the target but I can't get to "main()" and I get the following error:

ARM9_0: GEL: Error while executing OnTargetConnect(): Target failed to write 0x01C11138
at (*((unsigned int *) (0x01C11000+0x138))|=0x1) [OMAPL138_ARM_372MHz.gel:25]
at device_PLL0(0, 30, 1, 0, 1, 18, 5) [OMAPL138_ARM_372MHz.gel:414]
at Set_Core_372MHz() [OMAPL138_ARM_372MHz.gel:486]
at Core_372MHz_mDDR_150MHz() [OMAPL138_ARM_372MHz.gel:252]
at OnTargetConnect()

Now when testing the connection, I get:

[Start: Texas Instruments XDS100v2 USB Emulator]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\Yoel\AppData\Local\TEXASI~1\CCS\
TI\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Feb 18 2015'.
The library build time was '23:56:50'.
The library package version is '5.1.641.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS100v2 USB Emulator]

 

The Gel files worked great in the old board.

Any Ideas?

Thanks,

Yoel

  • Yoel,

    The fact the failure is on a GEL routine indicates this is most likely not an issue with CCS or the JTAG debugger itself (all low-level tests pass ok) but instead an issue with the hardware or the GEL file itself.

    The message says it fails to write to the memory mapped register at address 0x01C11138, which is the PLL controller region. In this case, I would first make sure the device is properly powered and all oscillators are stable and functional.

    Obviously this is just a tip, but the experts in the device forum may have additional insights. I will move this thread there.

    Hope this helps,
    Rafael
  • Hi Yoel,

    Do you have any other emulator ie XDS510 USB ?


    When I change it to Fixed 1Mhz freq, I can connect to the target but I can't get to "main()" and I get the following error:

    ARM9_0: GEL: Error while executing OnTargetConnect(): Target failed to write 0x01C11138
    at (*((unsigned int *) (0x01C11000+0x138))|=0x1) [OMAPL138_ARM_372MHz.gel:25]
    at device_PLL0(0, 30, 1, 0, 1, 18, 5) [OMAPL138_ARM_372MHz.gel:414]
    at Set_Core_372MHz() [OMAPL138_ARM_372MHz.gel:486]
    at Core_372MHz_mDDR_150MHz() [OMAPL138_ARM_372MHz.gel:252]
    at OnTargetConnect()

    Earlier, I've also faced the same problem with XDS100v2 emulator and this issue was gone once I set "Adaptive with user specified limit" to 1MHz.
    Also, I can debug XDS510USB without any problem.
  • Hello Titus,

    I do have XDS-560 USB emulator, I haven't used it because of the licensing, Do you think it can help?

    Yoel

  • Hi Titus,

    I tried connecting with the XDS560 and I got the following message:

    The value is '-181' (0xffffff4b).
    The title is 'SC_ERR_CTL_NO_TRG_CLOCK'.

    The explanation is:
    The controller has detected a dead JTAG clock.
    The user must turn-on or connect the JTAG clock for the target.

    Yoel
  • Hello Yoel,

    Have you verified your hardware connections on your board ? If possible, please share the JTAG section schematics.

    Regards,
    Senthil
  • Hi Senthil,

    There isn't much to show (see image attached), the lines go from the JTAG through a board-to-board connector to the LogicPD SOM.
    Pay attention that the EMU lines pull-ups are on the main board as for the Jtag connector on the daughter card.

    Regards,

    Yoel

  • Hello Yoel,

    I do not see pull down resistor on TRST line. Is it placed in some other page ?

    Also i would like you to check the design recommendations in the below links are followed in your design.

    Please ensure your emulator is working properly ? Did you check this emulator in some other board ?

    Regards,

    Senthil

  • Hi Senthil,

    Problem solved.

    We found a sneaky line that was badly named in the layout thus wasn't connected to the JTAG connector (RTCK/GP8[0]).

    We stitched it up and adaptive clocking works.

    Thanks for the help!

    Yoel 

  • Hello Yoel,

    Glad to hear that your JTAG interface is working fine.

    Thanks for the update.

    Regards,
    Senthil