Hello, we are developing a code in the ARM side on the OMAPL138 using SYS/BIOS.
We are also using the uPP interface to exchange data with a FPGA. The code inherits from another code developed for the DSP side and without OS, so we are not using the uPP driver but we are interfacing the uPP in register level.
We are using channel A to receive data that is being stored in the DDR2 and it usually works well. However, some times the transference stops and doesn't finish even though enable signal is active and clock is ok. We have realized that it happens e.g. when a new task is created. We have also seen that when another transference is queued in th DMA the first one seems to continue and the second one starts and finishes well.
We have changed the reception buffers that are now allocated in the L2 shared memory and that problem disappears. But we need that memory space to exchange data with the DSP so it can't be a final solution for us.
I wonder if it is a problem accessing the DDR2 by the uPP DMA because several tasks are running meanwhile.
Can anyone help us?
Thank you in advance.
Best regards.
