Hi,
My customer is now launching their HW using DA810.
Please assume the power up sequence is exactly following the description of Power-On Sequence in the data sheet.
That looks like :
- All of 1.2V (CVDD and related power supplies as RTC_CVDD and PLL0_VDDA) lane is powered on
- After CVDD is reached to the operating condition, DVDD is powered on. (Please note 1.8V power supply is not being used for USB0_VDDA18 because they does not use USB0)
- During the above power up sequence, /RESET pin is always being asserted (LOW). /RESET pin will be de-asserted once DVDD is reached to the operation condition.
So the question is, when CVDD is powered on, they saw some leak voltage (0.47V) on DVDD. Is this correct behavior ?
Best Regards,
Kawada