EDMA3 stop when McBSP0 RX and UART2 TX all use EDMA3!

Moving this to the AM1X forum.

Hi,

Thanks for your post.

I believe, EDMA3 stops due to priority considerations across TC0 and TC1 accessing event queues from appropriate CC's. When multiple masters are trying to access common shared resources, this priority value allows the system interconnect to arbitrate requests from different masters based on their priority. This priority assignment is determined in the Master Priority Registers (MSTPRI0-MSTPRI2) in the System Configuration Module.

For example, if there are events in Q0 and Q1 and the respective transfer controllers (TC0 and TC1) are ready to receive the next TR from the EDMA3CC, then the transfer requests associated with events in Q0 will get submitted to TC0 prior to any transfer requests associated with events in Q1 getting submitted to TC1. To make it more clear, at any given time, if there are outstanding events in multiple queues, when the transfer controller associated with the lower numbered queue is busy processing earlier transfer requests and the transfer controller associated with the higher numbered queue is idle, then the event in the higher numbered queue will be dequeued first. Due to this also, EDMA would stop since the queue is busy processing earlier request and the other queue which is idle would be dequeued first and unfortunately violating the dequeue priority rules by the EDMA3CC.

I would recommend you to poll for the errors, as the status of the errors could be read from the ERRSTAT registers, additionally if the error bits are enabled in the ERREN register, a bit set in the ERRSTAT will cause the error condition to interrupt the CPU. You can decide to enable/disable either or all error types.

To know more details on EDMA prioritization, please refer section 17.2.13 from the AM1806 TRM below:

http://www.ti.com/lit/ug/spruh83a/spruh83a.pdf

Thanks & regards,

Sivaraj K

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HI, Sivaraj K

i have test that if McBSP0 RX use CC0_TC0 and UART0 TX use CC0_TC1 EDMA3 will run normally and not stop, but if with UART1 TX or UART2 TX, EDMA3 will stop even priority of CC0_TC0 is set to 0 and CC0_TC1 is 6. Here the configuration of UART0 TX is same with UART1 TX and UART2 TX. System Interconnect shows that McBSP0 and UART1, UART2 are in SCR F7, but UART0 is in SCR2. Maybe this is the cause of EDMA stop? 

Hi,

Even I guess, the configuration of UART0TX would be different from UART1TX and UART2TX and cannot be same. May be, this could also be the cause of EDMA stop.

Kindly validate the UART0TX configuration since this is in different SCR2 compared to SCR F7 with respect to system interconnect.

Thanks & regards,

Sivaraj K

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