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ESD strick to OMAP-L137 w/ SDRAM

Kzk
Genius 5785 points
Other Parts Discussed in Thread: STRIKE, OMAP-L137

Hello,

I use OMAP-L137 with a external clock source and a 32-bit SDRAM. It seems that our system is susceptible to radiated noise during an ESD strike. L137 is uncontrolled during an ESD strike when the device uses the SDRAM. It's no problem except the SDRAM. Could you give me some advice? Do I also need the inpedance control on PCB for EMIFB?

Regards,
Kazu

  • 0
    TI__Mastermind 43660 points

    Hello Kazu,

    Are you having the external clock source as specified in section 2.1.5 System-Level ESD Immunity Usage Note of device errata ?

    Yes, it is always better to have controlled impedance on PCB for EMIFB and required spacing from the other interface signals would increase the noise immunity.

    You can also refer the below thread for clocking recommendation under ESD perspective.

    https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/381169


    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Genius 5785 points

    Hello Senthil,

    Thank you for your quick reply. Yes, I've read 2.1.5. I haven't controlled impedance on the PCB for EMIFB. It's working fine except ESD strike. Do you mean that the PCB increases the noise immunity If I control the impedance for EMIFB? I'm sorry, but I don't know very much about that. I guess that the impedance controlled is not increasing the noise immunity but rather increasing signal quality.

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Mastermind 43660 points

    Hello Kazu,

    Yes, the control impedance would increase the signal integrity but it would also increase the noise margin of the particular interface.

    What is the exact problem you are facing on SDRAM interface during ESD strike ?

    At which point the ESD strikes ? Is there any connectivity between the ESD strike point and the SoC/SDRAM ?

    Are you seeing this issue in one board or multiple boards ?

    Please ensure the PCB routing for proper reference plane etc.,

    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Genius 5785 points

    Hello Senthil,

    Thank you for your advice. When I hit an ESD gun vertically to the GND of every board, it's OK. But when there is no angle between the ESD gun and every board, it seems L137 is reset on its own. It looks like be affected by radiated noise during an ESD strike. I think SDRAM layout is better to be the short wiring and through the inner layers. In this case, could you tell me that controlled impedance for EMIFB is effective?

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Mastermind 43660 points
    Hello Kazu,

    The control impedance is always recommended for any interface and might reduce the effect of ESD. I would suggest you to redo the PCB layout of SDRAM interface with all ESD considerations in place.

    Regards,
    Senthil