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AM1808 VPIF Frame Interrupt Timing

g.f.
Guru 15510 points
Other Parts Discussed in Thread: AM1808

Hi,

I have questions about AM1808 VPIF interrupt.

The question is about frame interrupt.

I understand that the frame interrupt will be generated at the begining of frame.

But I want to know the timing of frame interrupt assertion.

1.Is frame interrupt timing same as VSYNC signal?

2.Does VPIF generate the frame interrupt at the timing of VSYNC rising-edge detection?

In TRM(spruh82a) page.1738 " 35.2.12.2 Field/Frame Interrupts to CPU ", it is written as follows:

//////////////////////////////////////////////////////////////////////////

The timing of the interrupt from the VPIF module is different from the timing of the V-sync.

//////////////////////////////////////////////////////////////////////////

but in page.1739, it is written as follows:

//////////////////////////////////////////////////////////////////////////

The interrupt signal from the VPIF is asserted when the vertical synchronization signal is received

//////////////////////////////////////////////////////////////////////////

So, I'm confusing.

best regards,

g.f.

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    In general, the frame/field interrupt timing and the VSYNC signal timing are not same. Actually, I belive, you have been misinterpretated with the above two statements from page no's 1738 and 1739.

    The above two statements are mentioned in a different context, firstly, in page no. 1738, "The timing of the interrupt from the VPIF module is different from the timing of the V-sync" which is actually a frame/field interrupt to CPU and this interrupt is generated when the last data transfer between the VPIF module and the VBUS is finished.  Here, the CPU cannot ignore this VPIF interrupt since it only make the processor identify the timing for updating the address register of the VPIF module.  So, this interrupt is completely different from the context, where the second statement "The interrupt signal from the VPIF is asserted when the vertical synchronization signal is received" in page no. 1739.

    The second statement from page no. 1739 is completely a different context, here the CPU has to ignore the first interrupt signal from the VPIF which is a big difference you could observe transparently. Here, the CPU uses this VPIF interrupt signal for

    the timing to read the stored data from the defined area in memory in addition to, uses for the time interval between each video frame but no incoming data is written in memory.

    Hope, it clarifies.

    Thanks & regards,

    Sivaraj K

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    Please click the Verify Answer button on this post if it answers your question

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  • 0 in reply to Sivaraj Kuppuraj
    Guru 15510 points
    Hi Sivaraj,

    Thank you for the reply.

    I'm sorry but let me ask again.

    From AM1808 TRM(spruh83a) page.1346 "31.2.12.2.1 Interrupt Condition",
    it said as follows:
    The VPIF generates the following events as conditions for interrupt assertion:
    * In CCD/CMOS capture mode, starting edge for first line of vertical pixel area.

    So, there are two cases for the frame interrupt.
    One is end of frame which is generated when last data transfer between the VPIF module nad VBUS is finished.
    And other is start of frame which is asserted by starting edge generated by VPIF.
    Is my understanding correct?

    By the way, in what timing the frame interrupt be asserted by starting edge
    which is written in "31.2.12.2.1 Interrupt Condition"?
    I wrote the timing of this interrupt in attached file, so can you please check the timing?

    best regards,
    g.f.
  • 0 in reply to Sivaraj Kuppuraj
    Guru 15510 points

    Sorry, I forgot to attach the file.VPIF Frame Interrupt.pdf

  • 0 in reply to g.f.
    TI__Mastermind 35645 points

    Hi,

    Yes, your understanding seems to be fine.

    The interrupt signal from the VPIF is asserted when the vertical synchronization signal is received. The first vertical synchronization signal is defined as the transition from the L10 line to the L11 line in the interlace mode or from the L4 line to the L5 line in the progressive mode.

    Please refer Figure 35-4 and Figure 35-5 from the TRM.

    Yes, the VPIF interrupt would be asserted at the timing of the starting edge of the V_SYNC signal as L10 line to L11 line in interlaced and L4  line to L5 line in progressive.

    Thanks & regards,

    Sivaraj K

    -------------------------------------------------------------------------------------------------------

    Please click the Verify Answer button on this post if it answers your question

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  • 0 in reply to Sivaraj Kuppuraj
    Guru 15510 points
    Hi Sivaraj,

    Thank you for the reply.

    But sorry, I'm still confusing.

    Let me ask again.

    I'm using Interlace Raw Capture mode.
    So, I guess starting edge of the V_SYNC signal as L10 line to L11 line in interlaced
    is not the case.

    As far as I understood, there are two interrupts generated for one frame
    which indicate the beginning of the frame and the end of the frame.
    One is generated at the starting edge for first line of vertical valid pixel area (indicate beginning of a frame).
    And other is last data transfer between the VPIF and VBUS (indicate the end of a frame).

    Can you tell me which timing will each Frame interrupt be generated by VPIF in Interlace Raw capture mode?
    If written in diagram, it will be very helpful to me to understand.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Mastermind 35645 points
    Hi,

    The VPIF interrupt would be asserted at the timing of the starting edge of the V_SYNC signal.

    Thanks & regards,
    Sivaraj K
  • 0 in reply to Sivaraj Kuppuraj
    Guru 15510 points
    Hi,

    I'm very sorry, but this is my last question.

    Do you mean that Frame Interrupt will be asserted in the timing of V-sync Starting edge and
    also last data transfer between the VPIF and VBUS in Raw Capture Mode?

    And do you mean that there are two Frame Interrupt(start/end of Frame) will be asserted in one Frame?

    best regards,
    g.f.