OMAP-L138 LCDC: maximum MCLK in LIDD mode

Neil Atkinson

Other Parts Discussed in Thread: OMAP-L138

Can anyone clarify when using the LCDC in LIDD mode, what is the minimum cycle time that MCLK can be set to?

According to the OMAP-L138 data sheet (sprs586h), the LIDD mode timing diagrams (page 214-221) show the clock period as parameter 1. However, this parameter is not listed in the LIDD mode timing requirements tables (Table 6-107 & 6-108).

Kind regards

Neil

over 8 years ago

0 Senthilkumar Srinivasan over 8 years ago

TI__Mastermind 43660 points

Hello Neil,

The cycle time specification for LCD_MCLK is not available in any of the external document. I will check if it is available in internal SoC specification and update you. Thanks for your patience until then.

Regards,
Senthil

0 Neil Atkinson over 8 years ago in reply to Senthilkumar Srinivasan

Intellectual 270 points

Hi Senthil

Thanks for looking into this.

I look forward to your response.

Kind regards

Neil

0 Senthilkumar Srinivasan over 8 years ago in reply to Neil Atkinson

TI__Mastermind 43660 points

Hello Neil,

There is no fixed cycle time available for LCD_MCLK. It is merely depends upon SYSCLK2 and the LCD_CTRL register CLKDIV value.

Moreover, LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability of control signals (CS, WE, OE, ALE) and output data.

Regards,
Senthil

0 Neil Atkinson over 8 years ago in reply to Senthilkumar Srinivasan

Intellectual 270 points

Hi Senthil

Many thanks for the confirmation of LCD_MCLK.

I acknowledge that there is a lot of programmable flexibility in the control signal timing. I was just concerned if there was a max limit to LCD_MCLK that was lower than SYSCLK2.

Kind regards

Neil

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OMAP-L138 LCDC: maximum MCLK in LIDD mode