AM1808 Kernel - I2C failure

Hi Yordan,

Thank you for the reply.

below are the I2C signals on the board.

SCL falling - crossing the absolute ratings (going below -0.5V).I believe AM1808 doesn't have such errata, so no such workaround implemented on the board.

But there are some series resistors near the I2C devices, changing those values had a little improvement in the peak voltage going below GND. I will try different values an will see any improvement.

and below is the SCL rising..

I think here need to worry about absolute ratings. As noise filters implemented in the chip, do I need worry about I2C failures because of this ringing/noise?

What could else be reason for the random I2C failure?

Regards,

Srinivas J

Hi,

We observed SCL is low around 32ms in a transaction (Single-Byte Read) between AM1808 and TMP431, which can reset I2C interface of TMP431.

What is holding SCL low? AM1808 or TMP431?

As TMP431 can also hold SCL low, how long it can hold low?

Regards,

Srinivas J

There's no limit in the I2C specification in terms of how long SCL can be held low.  A typical instance where SCL would be held low is when the master is performing a read, the slave may temporarily hold SCL low while it is fetching the corresponding data to send back. 

SMBus has a 32ms timeout.  The TMP431 looks like it implements SMBus and so my best guess of what's happening here is that the TMP431 is holding SCL low for some reason (which I think is what you need to figure out to resolve the issue) and ultimately causes itself to timeout after 32ms.

Where in the sequence exactly is the clock stretching happening?  If it is immediately before the TMP431 would be responding with the data, then I think this all fits...

Hi Brad,

The I2C transaction is as below...

Start -> TMP431 address -> W ->ACK ->Pointer Register Byte -> ACK ---> delay us to ms ---> Start -> TMP431 address -> R -> ACK -> Data

from the above capture (continuation of the address write), the delay (where SCL is low) between address write and data read is more than 32ms, where the timeout happens and the TMP431 interface is in reset, no ACK from TMP431.The I2C transaction fail reported by AM1808.

Is there anything to suspect from AM1808 side?

Regards,

Srinivas J

Srinivas Jagarapu said:

Is there anything to suspect from AM1808 side?

The only thought that comes to mind here would be if you're seeing some kind of major interrupt latency.  You might try running a test with as little software as possible running to see if the issue is still present.  If not, that might indicate that this relates to interrupt jitter.

Hi Brad,

In "Table 22-1. Operating Modes of I2C Peripherals" from AM1808 reference manual,

" Master-transmitter mode: The clock pulses are inhibited and I2Cx_SCL is held low when the intervention of the processor is required (XSMT = 0 in ICSTR) after data has been transmitted."

This is exceeding 32ms and causing timeout for TMP431, Is there any way AM1808 to stop holding SCL low?

Regards,

Srinivas J

On having a fresh look, I think you might be right that it is the AM1808 holding the line low.  However, if that is the case, this is likely due to interrupt latency.  Unfortunately, I don't have any easy answers in terms of how to address it.