OMAPL138 EMDA3 concurrent transfer

Hi Sivaraj,

Thanks for your reply. Your answer is what I thought previously. But I got an opposite result. Let me describe my experiment.

I use a GP2_x of input signal to trigger a SPI DMA transfer (4*16-bit data) previously and it works well. SPI clock signal was generated about 0.7us after GP2_x's rising edge and four 16-bit data can be watched via Osilloscope sequentially. SPI DMA moves data between SPI peripheral and L2 RAM. It utilizes EDMA30CC0 and EDMA30TC0. Because GPIO BANK2 EVT belongs to EDMA30CC0.

Now I use another GP6_x pin to trigger a EMIFA DMA transfer to move data from ext. FPGA to ext. DDR. This DMA utilizes EDMA31CC0 and EDMA31TC0. GPIO BANK6 EVT belongs to EDMA31CC0.

Everything is OK but when the two DMA overlaps each other. By observing waveforms from Osilloscope, SPI clock signal was generated far away from GP2_x's rising edge and 4 16-bit SPI data was seperated into two group with an obvious abnormal gap between the 2nd 16-bit data and 3rd one.

Make sure that no overlap exists and SPI data runs normally.

Should the SCR be responsible for this? The two DMA uses a same SCR just like two cars drive on a single road.

Thanks and Regards,

Jim

I updated two oscilloscope waveform pictures here.

DMA issue 05-.jpg (1st picture) is a normal one when two DMAs were not overlaped.

DMA issue 00-.jpg (2nd one) is an abnormal one when EMIFA DMA started at the latter part of 1st 16bit SPI DMA transfer which can be told from SPI CLK waveform. And then the rest of SPI DMA data (3*16bit) was interrupted until EMFIA DMA was done (CS signal turned high).

My SPI DMA is triggered by GP2_0 and then utilizes EDMA3's 'chain' transfer logic. EMIFA DMA is triggered by GP6_12. Use a static PaRAM configuraiton.

So can these two pictures prove that OMAP-DSP core cant support DMA transfers more than 1  to be executed at a same time / simultaneously?

Another question. In picture one there is a 'another question' text mark. It shows CS signal became inactive and then active again. In fact, I configured EMIFA DMA's PaRAM set as a 20*16bit transfer. The mark point was generated after 16*16bit data been transferred. I also configured CFGCHIP0.EDMA30TC0DBS, CFGCHIP0.EDMA30TC1DBS and CFGCHIP1.EDMA31TC0DBS as '32byte'.

What's the problem?

Sivaraj Kuppuraj said:

Hi,

Thanks for your post.

In case, if CC0 belongs to TC0, and with in TC0, both the transfers A & B cannot possible to start at same time but if you trigger an event corresponding to DMA channel belongs to different TC1, then the transfers of A & B corresponding to CC0,TC0 and CC1, TC1 could start independantly. It is obvious from this, that different channels mapped to different TC's can act independently and can start transfer at same time.

Thanks & regards,

Sivaraj K

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hi Sivaraj, any suggestion about my puzzle?