Hi,
We are interfacing an ADS1278EVM to the lcdkc6748 using J16 Camera SPI1 port. We are also using C6748_StarterWare_1_20_03_03 platform. Our clock signal(sampling clock-4MHz) wich is the same serial clock signal (SPI1_CLK) comes from a signal generator, we are also using a GPIO port to sensing the DRDY signal from conversor for commnication starts.
I want to configure the C6748lck as slave mode but I do not have any data. The conversor has a 24 bit resolution So I want to receive two 12 bits streams between samples. I only enable one channel.
Please could you have a look into my code and write where is the mistake? I can not see where the mistake is.