This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAPL138 with Asynchronous External Dual Port Memory and EMIFA interface problem

Other Parts Discussed in Thread: OMAPL138, OMAP-L138

We have failed units which do not pass a memory address/address complement test (stock bits at certain addresses) on an asynchronous Dual Port Memory.

Setup:

   Asynchronous DPM memory interfaced to OMAPL138 thru EMIFA.

   External DPM memory interfaced to DSK5510 thru EMIF controller.

   Memory tests executed by loading test software via JTAG on OMAPL138 DSP core, and to DSK5510 evaluation board (tests are executed separately).

   Cache is disabled on both systems.

   Code is compiled without optimizations, and pointers to memory addresses to test are volatile.

 

Behavior:

   Test software on both interfaces (internally and externally, OMAPL138 and DSK5510 respectively) fail to detect the memory errors.

   Both tests write a block of memory of 128KB then read back the expected pattern successfully (which should fail).

   When a long delay is implemented after the memory block is written (and before reading) tests on both interfaces detect the errors successfully.

  

Questions:

   Can the EMIF interfaces of both/either system (OMAPL138 and DSK5510) cache data written to the DPM memory?

   Can this be a transient memory error (which shows after a certain amount of time has elapsed since data is written to the address)?