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OMAP-L138 TI Bootloader sequential read on SPI Flash memory

Other Parts Discussed in Thread: OMAP-L138, OMAPL138, AM1808

Hello,

Using the TI Bootloader of the OMAPL-138 I'm loading a software in the ARM core, but when I've observed the SPI clock and chip select signals I have seen that between each words of 8 bit there is a pause in the transmission.

7 words of 8 bit :

zoom on one word of 8 bit :

Configuration of the AISgen tool :

I don't understand where theses pauses come from and I would like to get rid of them, can you help me configure correctly the AISGen tool ?

Best Regards

Arthur CARTIER

  • Hi Yordan,

    Thank you for your fast answer, but I've already read theses documents and didn't saw the explanation on why there is a pause in between each words.
    In addition we are not using this U-Boot or UBL file but only the small bootloader that is included in the OMAP-L138 and can interpret an AIS script.

    Best Regards
    Arthur CARTIER
  • Hi Arthur,

    You're correct. There the links explain the ais tool configuration for signing the u-boot.

    In addition we are not using this U-Boot or UBL file but only the small bootloader that is included in the OMAP-L138 and can interpret an AIS script.

    Could you elaborate? Are you using the MCSDK u-boot, which can be AIS signed & flashed on the board, as a primary bootloader?
    If you're not using the MCSDK (linux release for OMAP-L138), could you point which sdk is this?

    Best Regards,
    Yordan
  • Hi Yordan,

    We are not using any sdk, but my question is not yet how to configure this software that we have developed, converted into an AIS script through AISgen and flashed in an SPI memory on the board.

    My question is related to the bootloader that is embedded in the read-only memory, read the boot pins to select the memory/interface to boot from and will read and interpret from this memory/interface an AIS script  that has been previously flashed. (this bootloader is described in the document SPRAB41 http://www.ti.com/lit/pdf/sprab41)

    The 2 chronogram That I have included in my first message shows that when the OMAP-L138 bootloader (located in the ROM) read the AIS script (containing our software) from the memory, it make a pause in between each word (of 8 bit).

    And I would like to first understand where these pause come from and then if it is possible to suppress them.

    Best regards

    Arthur

  • Arthur,

    Can you please configure PLL0 (and PLL1 if you are using DDR) so that the cores are configured at 300 Mhz or 456 Mhz. (check device variant). At the moment it looks like the Device is booting in PLL bypass state, which is the DSP and ARM core will be running at 25Mhz and you are trying to run the SPI clock at 6.25 Mhz.

    What flash device have you connected to OMAPL138. Is it a EEPROM or a NOR flash device. Can you confirm that you have connected the SPI flash media in 4 pin mode with SIMO, SOMI, CS, CLK pins on CS0.

    I have looked at the Bootloader source code and don`t see any pauses inserted. The CS is always low so it appears that the bootloader is setting the read mode to sequential Read. I think the pauses may be cause the Bootloader is executing at 25 Mhz instead of device speed grade.

    Regards,
    Rahul
  • Hello Rahul,

    Rahul Prabhu said:

    Can you please configure PLL0 (and PLL1 if you are using DDR) so that the cores are configured at 300 Mhz or 456 Mhz. (check device variant). At the moment it looks like the Device is booting in PLL bypass state, which is the DSP and ARM core will be running at 25Mhz and you are trying to run the SPI clock at 6.25 Mhz.

    I checked the Configure PLL0 on the "General" tab of the AISgen tool and let the default values in the "PLL0" tab, which give us core running at 300MHz and an SPI module clock at 150 MHz, then I set the SPI clock successively at 6MHz (screen 1) and 30MHz (screen 2), unfortunately their are still pause in between each words (8 bits). This software is located exclusively in the ARM RAM and the Shared RAM.

    screen 1:

    screen 2 :

    Rahul Prabhu said:
    What flash device have you connected to OMAPL138. Is it a EEPROM or a NOR flash device. Can you confirm that you have connected the SPI flash media in 4 pin mode with SIMO, SOMI, CS, CLK pins on CS0.

    The flash we are using is a NOR Flash (M25P128 by numonyx) and have connected it using the 4 pin mode with SIMO, SOMI, CS, CLK pins on CS0.

    Rahul Prabhu said:

    I have looked at the Bootloader source code and don`t see any pauses inserted. The CS is always low so it appears that the bootloader is setting the read mode to sequential Read.

    Is the source code of the Bootloader available fro customers ?

    Best Regards

    Arthur

  • Arthur,

    Thanks for your patience. I am checking on this issue with the design team and the Bootloader author and will post a response as soon as I hear from them. In the meantime can you let us know if you have tried this setup without sequential read and does that also have pauses between subsequent reads or is that setup working as expected with your flash.

    Arthur Cartier said:
    Is the source code of the Bootloader available fro customers ?

    No, we don`t distribute the Bootloader source to customers.

    Regards,

    Rahul

  • Arthur,

    The ROM author for this device provided the following response.

    As the time between successive 8-bit transfers is reduced when you increase the CPU clock, we can only conclude that this delay between transfers is the actual time of the ROM execution between read operations (each of which happens as a distinct 8-bit clock in/out). Because the ARM ROM is running with the cache disabled, I’m not too surprised by this. From the boot benchmark data, the SPI boot on DSP vs ARM comparison showed that cache has a measurable impact.
    processors.wiki.ti.com/.../OMAP-L138_Boot_Benchmarks

    The note at the end of the wiki page is useful: “For larger boot images on OMAP-L138/AM1808, it would be beneficial to enable the cache through AIS commands. Future versions of AISgen will provide this option.”

    Also note, we are using polling to figure out when the SPI transfer is complete, so there is some bus time spent reading from the peripheral. Add that to the instruction fetches which have to go all the way to the ROM for every instruction, which may also be some of the other reasons contributing to those delays


    Hope this helps.

    Regards,
    Rahul