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456Mhz Board Flash Problem using CCS JTAG Method

Senthil Kumar11061
Expert 1270 points
Part Number: OMAPL138B-EP
Other Parts Discussed in Thread: OMAPL138

Tool/software: Code Composer Studio

We have Custom Made OMAPL138 Board which operating at 456Mhz.

 

We are Using CCS JTAG Method to Flash the Pgm

 

We have created simple LED Toggle Application  which is working  using CCS Debugging

 

If I Flash the Same .out File  using CCS JTAG  Not Working

 

I am follow the Procedure as follows

 

  1. Generate the Boot.out file From Starter ware Boot loader Project and Enter the ARM entry point as

unsigned int entryPoint = 0xc1080000;

unsigned int DspEntryPoint = 0;

 

  1. Generate the Boot.ais File from AisGen Tool, Here I enclosed the AisGen Config File
  2. Generate the HDS_ARM_GPIO_TEST.out file  from the Led Toggle Application Project
  3. Genetae the HDS_ARM_GPIO_TEST.bin file from ttool out2rprc
  4. Using Nand Writer Project  I flash the boot.ais file  HDS_ARM_GPIO_TEST.bin  file

 OMAPL138_LCDK_AISGen_Config_456MHz.cfg

I not find out the Fault in config file   anyone suggest me where is the problem?

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the RTOS team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0
    TI__Guru** 114410 points
    Senthil,

    Is your custom board based on our evaluation platform LCDKC6748 ? If yes, can you confirm if the NAND is 8 bit or 16 bit and what is the part number? did you setup the NAND_WIDTH in the flash writer correctly ? Also, after you flash the NAND, have you changed the boot switches to NAND boot ? the AID Gen config that you are using setup the clock, DDR and pinmx so it will need to be changed if you are custom board is not using the same input clock or DDR part.

    Please test this setup on the LCDK platform and confirm that the boot is working as expected.

    another good way to debug boot is to connect to the core after boott up and look at the program counter of the core. Is this in ROM bootloader memory, or in the secondary bootloader memory or in the application memory location. this narrows down the issue to a specific boot component.

    Also, we provide a debug GEL file to analyze system state when the boot fails:
    processors.wiki.ti.com/.../OMAP-L1x_Debug_Gel_Files

    Run this when your boot fails and report the log here for us to analyze.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Expert 1270 points

    Our Custom Board Based on LCDK L138 . Everything Same Except


    DDR2 SDRAM part No. used in TI OMAP L138 Dev. Kit, W971GG6KB-25

    DDR2 SDRAM part No. used in our Board , W9725G6KB-25I

    We are using NAND 16
    Part Number is MT29F4G16ABADAH4-D

    We Set NAND_WIDTH as 16 in Flash Writer Correctly

    We are using only NAND Boot method only

    we tested the this AISGen cfg file in LDCK OMAP Board but not working.

    But we tried the TI Provided Aisgen cfg file for 300Mhz its working.

    We are using Starterware Boot Loader to generate the Boot.out file

    Here i enclosed the CCS Project of Starter wareBootLoder_ourboards.zip Boot loader

    We are using 

    Code Composer Studio

    Version: 7.1.0.00016

  • 0 in reply to Senthil Kumar11061
    TI__Guru** 114410 points

    Senthil,

    When you updated from 300 Mhz to 456MHz, did you ensure that all your clocks are within the data sheet range ?

    We provide a clocking spreadsheet to simulate the clocks so you can adjusst the PLL dividers for SYSCLK that driver the EMIFA module and update the AISGen configuration accordingly. The other thing to try would be to see if images can run from shared on chip memory instead of DDR2, this eliminates the external memory configuration from being the root cause of the issue.

    Have you also checked the log in from the Debug GEL file, that captures device system states when boot fails:

    processors.wiki.ti.com/.../OMAP-L1x_Debug_Gel_Files

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Expert 1270 points

    My GEL  OUTPUT

    C674X_0: GEL Output:
    ---------------------------------------------
    C674X_0: GEL Output: | Device Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_02 = 0x00000010
    C674X_0: GEL Output: DEV_INFO_03 = 0x00000035
    C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
    C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6128884-7-58-18
    C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,13770
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
    C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
    C674X_0: GEL Output: DEV_INFO_21 = 0x3830306B
    C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_24 = 0x0701203A
    C674X_0: GEL Output: DEV_INFO_25 = 0x005D84F4
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
    C674X_0: GEL Output: DEV_INFO_26 = 0x6B940005
    C674X_0: GEL Output:

    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | BOOTROM Info |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: ROM ID: d800k008
    C674X_0: GEL Output: Silicon Revision 2.1
    C674X_0: GEL Output: Boot pins: 16
    C674X_0: GEL Output: Boot Mode: NAND 16
    C674X_0: GEL Output:
    ROM Status Code: 0x00000001
    Description:C674X_0: GEL Output: DSP was put to sleep
    C674X_0: GEL Output:
    Program Counter (PC) = 0x00700000
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | Clock Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLLs configured to utilize crystal.
    C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    C674X_0: GEL Output:
    C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
    C674X_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
    C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
    C674X_0: GEL Output: and then reload.
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PLL0 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLL0_SYSCLK1 = 24 MHz
    C674X_0: GEL Output: PLL0_SYSCLK2 = 12 MHz
    C674X_0: GEL Output: PLL0_SYSCLK3 = 8 MHz
    C674X_0: GEL Output: PLL0_SYSCLK4 = 6 MHz
    C674X_0: GEL Output: PLL0_SYSCLK5 = 8 MHz
    C674X_0: GEL Output: PLL0_SYSCLK6 = 24 MHz
    C674X_0: GEL Output: PLL0_SYSCLK7 = 4 MHz
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PLL1 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLL1_SYSCLK1 = 24 MHz
    C674X_0: GEL Output: PLL1_SYSCLK2 = 24 MHz
    C674X_0: GEL Output: PLL1_SYSCLK3 = 24 MHz
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PSC0 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output:
    C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 0
    C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0
    C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
    C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 0
    C674X_0: GEL Output: Module 4: SPI 0 STATE = 0
    C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 0
    C674X_0: GEL Output: Module 6: AINTC STATE = 3
    C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
    C674X_0: GEL Output: Module 9: UART 0 STATE = 0
    C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
    C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
    C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
    C674X_0: GEL Output: Module 13: PRUSS STATE = 0
    C674X_0: GEL Output: Module 14: ARM STATE = 0
    C674X_0: GEL Output: Module 15: DSP STATE = 3
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PSC1 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output:
    C674X_0: GEL Output: Module 0: EDMA3CC (1) STATE = 0
    C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 0
    C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 0
    C674X_0: GEL Output: Module 3: GPIO STATE = 0
    C674X_0: GEL Output: Module 4: UHPI STATE = 0
    C674X_0: GEL Output: Module 5: EMAC STATE = 0
    C674X_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 0
    C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0
    C674X_0: GEL Output: Module 8: SATA STATE = 0
    C674X_0: GEL Output: Module 9: VPIF STATE = 0
    C674X_0: GEL Output: Module 10: SPI 1 STATE = 0
    C674X_0: GEL Output: Module 11: I2C 1 STATE = 0
    C674X_0: GEL Output: Module 12: UART 1 STATE = 0
    C674X_0: GEL Output: Module 13: UART 2 STATE = 0
    C674X_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
    C674X_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
    C674X_0: GEL Output: Module 16: LCDC STATE = 0
    C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
    C674X_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
    C674X_0: GEL Output: Module 19: UPP STATE = 0
    C674X_0: GEL Output: Module 20: eCAP (all) STATE = 0
    C674X_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
    C674X_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
    C674X_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
    C674X_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
    C674X_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
    C674X_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
    C674X_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
    C674X_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
    C674X_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

    We are using Starterware Bootloader Project code as its no changes any changes Required ?

  • 0 in reply to Senthil Kumar11061
    TI__Guru** 114410 points
    The Debug GEL file log shows Program counter (PC) is at base address of DSP ROM. This indicates the ROM bootloader on the device has not started executing, device clocks (PLL) are still in bypass state (default reset state). you will need to check power up sequence and the power management circuits on your device to see why the DSP is not powering up. The ROM Status code indicates that DSP is still in sleep/not power up. The boot mode configuration is correct so the ROM should start executing and atleast try to read the NAND ID, it can`t be hung at the base of the ROM bootloader.

    This most likely doesn`t appear to be a software related issue as far as I can tell.
  • 0 in reply to Rahul Prabhu
    TI__Guru* 78325 points
    Hi Senthil

    can you clarify what you meant by
    >>But we tried the TI Provided Aisgen cfg file for 300Mhz its working.


    Is your custom board working with NAND flash boot , at 300 MHz using TI or your own AISCFG , but just not working on 456 MHz?

    If so, can you make sure your power supply design is correct and you have 1.3V CVDD and RVDD programmed appropriately?

    If you think your power supply design is correct, as Rahul pointed out i would recommend ensuring your PLL/clock settings are correct for 456 MHz.
    I would also recommend manually probing the NAND CS and other signals to see what is happening between a working 300 MHz vs non working 456 configuration on your custom board.

    Hope this helps.
    Regards
    Mukul
  • 0 in reply to Rahul Prabhu
    Expert 1270 points
    We have already Generated Final Image Files .ais and .bin ,that files work with Our Board. So there will be no issue with Hardware.

    it mostly Image Generation and Config Issue.

    if we generated the above said file the OMAP Not Running.

    we don't have confirm working Starter ware Boot Loader Project Files and AisGen .cfg File For 456Mhz Operation.
    Now we have only Arm Project Source Code and DSP Project CCS Source Code.
  • 0 in reply to Mukul Bhatnagar
    Expert 1270 points
    any Modification required for Starter ware Boot loader CCS Project for 456Mhz ?
  • 0 in reply to Senthil Kumar11061
    TI__Guru* 78325 points
    Senthil
    It appears that you are debug gel file output is from connecting the DSP side CCS.
    If you have OMAPL138 (not c6748) can you try to share the debug gel output from aRM side, once your boot is not successful?

    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Expert 1270 points
    ARM9_0: GEL Output:
    ---------------------------------------------
    ARM9_0: GEL Output: | Device Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_02 = 0x00000010
    ARM9_0: GEL Output: DEV_INFO_03 = 0x00000035
    ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6128884-7-58-18
    ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,13770
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003
    ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_20 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_21 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864
    ARM9_0: GEL Output: DEV_INFO_23 = 0x3830306B
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_24 = 0x0701203A
    ARM9_0: GEL Output: DEV_INFO_25 = 0x005D84F4
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_26 = 0x6B940005
    ARM9_0: GEL Output:

    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | BOOTROM Info |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: ROM ID: d800k008
    ARM9_0: GEL Output: Silicon Revision 2.1
    ARM9_0: GEL Output: Boot pins: 16
    ARM9_0: GEL Output: Boot Mode: NAND 16
    ARM9_0: GEL Output:
    ROM Status Code: 0x00000000
    Description:ARM9_0: GEL Output: No error
    ARM9_0: GEL Output:
    Program Counter (PC) = 0x80005DF4
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | Clock Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLLs configured to utilize crystal.
    ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
    ARM9_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
    ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,
    ARM9_0: GEL Output: and then reload.
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK3 = 100 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (0) STATE = 0
    ARM9_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0
    ARM9_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
    ARM9_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
    ARM9_0: GEL Output: Module 4: SPI 0 STATE = 0
    ARM9_0: GEL Output: Module 5: MMC/SD 0 STATE = 0
    ARM9_0: GEL Output: Module 6: AINTC STATE = 3
    ARM9_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
    ARM9_0: GEL Output: Module 9: UART 0 STATE = 0
    ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
    ARM9_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
    ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
    ARM9_0: GEL Output: Module 13: PRUSS STATE = 0
    ARM9_0: GEL Output: Module 14: ARM STATE = 3
    ARM9_0: GEL Output: Module 15: DSP STATE = 0
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (1) STATE = 0
    ARM9_0: GEL Output: Module 1: USB0 (2.0) STATE = 3
    ARM9_0: GEL Output: Module 2: USB1 (1.1) STATE = 0
    ARM9_0: GEL Output: Module 3: GPIO STATE = 0
    ARM9_0: GEL Output: Module 4: UHPI STATE = 0
    ARM9_0: GEL Output: Module 5: EMAC STATE = 0
    ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3
    ARM9_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 8: SATA STATE = 0
    ARM9_0: GEL Output: Module 9: VPIF STATE = 0
    ARM9_0: GEL Output: Module 10: SPI 1 STATE = 0
    ARM9_0: GEL Output: Module 11: I2C 1 STATE = 0
    ARM9_0: GEL Output: Module 12: UART 1 STATE = 0
    ARM9_0: GEL Output: Module 13: UART 2 STATE = 3
    ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 16: LCDC STATE = 0
    ARM9_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
    ARM9_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
    ARM9_0: GEL Output: Module 19: UPP STATE = 0
    ARM9_0: GEL Output: Module 20: eCAP (all) STATE = 0
    ARM9_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
    ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
    ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
    ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
    ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
    ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
    ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
    ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
    ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3
  • 0 in reply to Senthil Kumar11061
    TI__Guru** 114410 points

    If you look at the ROM status and the Program counter, you will notice that the device did boot from NAND and is executing code in On chip SRAM which means that the ROM bootloader got into the secondary bootloader. 

    In this state, you can load the symbols from .out of the Starterware bootloader and check where the core is hung at. When you connected the emulator can you confirm that you can go to DDR memory location in Memory browser and read and write correctly. IF not the SBL might be failing as DDR memory has not been setup correctly.

    the starterware bootloader as you know is a two stage boot. The first stage is MLO (secondary bootloader ) is copied by ROM bootloader to on chip RAM and the second stage is the secondary bootloader loads the actual ARM + DSP application after initializing DDR memory and setting up the rest of the device initialization. The above log indicates that first stage is working correctly and ROM loaded the SBL in on chip RAM, you need to check what is causing the core to hang in the secondary bootloader

    Now that you have the bootloader aand the application flashed in NAND, the other way to debug this is to load the .out for the Starterware bootloader and see if it is able initialize the SOC and load the multicore image from flash and pass control to your application.



    Regards,
    Rahul

    PS:  This log indicates that you are setting the PLL to 300 Mhz not 456 Mhz .Did you provide a log of the 300 Mhz usecase when the boot passes. Can you provide the log when it fails to boot.

  • 0 in reply to Mukul Bhatnagar
    Expert 1270 points
    ARM9_0: GEL Output:
    ---------------------------------------------
    ARM9_0: GEL Output: | Device Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_02 = 0x00000010
    ARM9_0: GEL Output: DEV_INFO_03 = 0x00000035
    ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6128884-7-58-18
    ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,13770
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003
    ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_20 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_21 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864
    ARM9_0: GEL Output: DEV_INFO_23 = 0x3830306B
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_24 = 0x0701203A
    ARM9_0: GEL Output: DEV_INFO_25 = 0x005D84F4
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_26 = 0x6B940005
    ARM9_0: GEL Output:

    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | BOOTROM Info |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: ROM ID: d800k008
    ARM9_0: GEL Output: Silicon Revision 2.1
    ARM9_0: GEL Output: Boot pins: 16
    ARM9_0: GEL Output: Boot Mode: NAND 16
    ARM9_0: GEL Output:
    ROM Status Code: 0x00000000
    Description:ARM9_0: GEL Output: No error
    ARM9_0: GEL Output:
    Program Counter (PC) = 0x80005DF4
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | Clock Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLLs configured to utilize crystal.
    ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
    ARM9_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
    ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,
    ARM9_0: GEL Output: and then reload.
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK3 = 100 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (0) STATE = 0
    ARM9_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0
    ARM9_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
    ARM9_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
    ARM9_0: GEL Output: Module 4: SPI 0 STATE = 0
    ARM9_0: GEL Output: Module 5: MMC/SD 0 STATE = 0
    ARM9_0: GEL Output: Module 6: AINTC STATE = 3
    ARM9_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
    ARM9_0: GEL Output: Module 9: UART 0 STATE = 0
    ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
    ARM9_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
    ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
    ARM9_0: GEL Output: Module 13: PRUSS STATE = 0
    ARM9_0: GEL Output: Module 14: ARM STATE = 3
    ARM9_0: GEL Output: Module 15: DSP STATE = 0
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (1) STATE = 0
    ARM9_0: GEL Output: Module 1: USB0 (2.0) STATE = 3
    ARM9_0: GEL Output: Module 2: USB1 (1.1) STATE = 0
    ARM9_0: GEL Output: Module 3: GPIO STATE = 0
    ARM9_0: GEL Output: Module 4: UHPI STATE = 0
    ARM9_0: GEL Output: Module 5: EMAC STATE = 0
    ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3
    ARM9_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 8: SATA STATE = 0
    ARM9_0: GEL Output: Module 9: VPIF STATE = 0
    ARM9_0: GEL Output: Module 10: SPI 1 STATE = 0
    ARM9_0: GEL Output: Module 11: I2C 1 STATE = 0
    ARM9_0: GEL Output: Module 12: UART 1 STATE = 0
    ARM9_0: GEL Output: Module 13: UART 2 STATE = 3
    ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 16: LCDC STATE = 0
    ARM9_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
    ARM9_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
    ARM9_0: GEL Output: Module 19: UPP STATE = 0
    ARM9_0: GEL Output: Module 20: eCAP (all) STATE = 0
    ARM9_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
    ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
    ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
    ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
    ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
    ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
    ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
    ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
    ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3
  • 0 in reply to Senthil Kumar11061
    TI__Guru* 78325 points

    Hi Senthil

    I think either you forgot to attach the debug gel file log for 456 MHz again or you think you are trying to configure to 456 MHz , but it is still being set as 300 MHz.

    Your last log still shows 300 MHz, which should be your "passing" case

    See the following

    ARM9_0: GEL Output: ---------------------------------------------

    ARM9_0: GEL Output: | PLL0 Information |

    ARM9_0: GEL Output: ---------------------------------------------

    ARM9_0: GEL Output:

    ARM9_0: GEL Output: PLL0_SYSCLK1 = 300 MHz

    ARM9_0: GEL Output: PLL0_SYSCLK2 = 150 MHz

    ARM9_0: GEL Output: PLL0_SYSCLK3 = 100 MHz

    ARM9_0: GEL Output: PLL0_SYSCLK4 = 75 MHz

    ARM9_0: GEL Output: PLL0_SYSCLK5 = 100 MHz

    ARM9_0: GEL Output: PLL0_SYSCLK6 = 300 MHz

    ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz

    ---

    If your cfg file was what you attached in your first message, that does not seem to be configuring it for 300 MHz.

    You can look at the below that i pulled up from 

    Clock Type=0

    PLL0 Pre Divider=2

    PLL0 Multiplier=25

    PLL0 Post Divider=1

    PLL0 Div1=1

    PLL0 Div3=3

    PLL0 Div7=6

    See if this or please clarify the points Rahul has requested.

    Thanks 

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    TI__Guru* 78325 points
    Hi
    Were you able to resolve this issue?

    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Expert 1270 points
    Hi,
    Now i have made some changes and Getting Debug Gel out as follows
    if i want to start correct bootloader operation ,what are the changes Required?

    Working One:
    ARM9_0: GEL Output:
    ---------------------------------------------
    ARM9_0: GEL Output: | Device Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_02 = 0x00000010
    ARM9_0: GEL Output: DEV_INFO_03 = 0x00000035
    ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6128884-7-58-18
    ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,13770
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003
    ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_20 = 0x30303864
    ARM9_0: GEL Output: DEV_INFO_21 = 0x3830306B
    ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864
    ARM9_0: GEL Output: DEV_INFO_23 = 0x3830306B
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_24 = 0x0701203A
    ARM9_0: GEL Output: DEV_INFO_25 = 0x005D84F4
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_26 = 0x6B940005
    ARM9_0: GEL Output:

    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | BOOTROM Info |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: ROM ID: d800k008
    ARM9_0: GEL Output: Silicon Revision 2.1
    ARM9_0: GEL Output: Boot pins: 16
    ARM9_0: GEL Output: Boot Mode: NAND 16
    ARM9_0: GEL Output:
    ROM Status Code: 0x00000000
    Description:ARM9_0: GEL Output: No error
    ARM9_0: GEL Output:
    Program Counter (PC) = 0xC1086298
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | Clock Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLLs configured to utilize crystal.
    ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
    ARM9_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
    ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,
    ARM9_0: GEL Output: and then reload.
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL0_SYSCLK1 = 456 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK2 = 228 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK3 = 228 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK4 = 114 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK5 = 152 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK6 = 456 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3
    ARM9_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3
    ARM9_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
    ARM9_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
    ARM9_0: GEL Output: Module 4: SPI 0 STATE = 3
    ARM9_0: GEL Output: Module 5: MMC/SD 0 STATE = 0
    ARM9_0: GEL Output: Module 6: AINTC STATE = 3
    ARM9_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
    ARM9_0: GEL Output: Module 9: UART 0 STATE = 3
    ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
    ARM9_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
    ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
    ARM9_0: GEL Output: Module 13: PRUSS STATE = 0
    ARM9_0: GEL Output: Module 14: ARM STATE = 3
    ARM9_0: GEL Output: Module 15: DSP STATE = 3
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (1) STATE = 3
    ARM9_0: GEL Output: Module 1: USB0 (2.0) STATE = 3
    ARM9_0: GEL Output: Module 2: USB1 (1.1) STATE = 3
    ARM9_0: GEL Output: Module 3: GPIO STATE = 3
    ARM9_0: GEL Output: Module 4: UHPI STATE = 0
    ARM9_0: GEL Output: Module 5: EMAC STATE = 0
    ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3
    ARM9_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3
    ARM9_0: GEL Output: Module 8: SATA STATE = 0
    ARM9_0: GEL Output: Module 9: VPIF STATE = 0
    ARM9_0: GEL Output: Module 10: SPI 1 STATE = 0
    ARM9_0: GEL Output: Module 11: I2C 1 STATE = 0
    ARM9_0: GEL Output: Module 12: UART 1 STATE = 3
    ARM9_0: GEL Output: Module 13: UART 2 STATE = 3
    ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 16: LCDC STATE = 0
    ARM9_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
    ARM9_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
    ARM9_0: GEL Output: Module 19: UPP STATE = 0
    ARM9_0: GEL Output: Module 20: eCAP (all) STATE = 0
    ARM9_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
    ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
    ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
    ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
    ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
    ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
    ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
    ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
    ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

    C674X_0: GEL Output:
    ---------------------------------------------
    C674X_0: GEL Output: | Device Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_02 = 0x00000010
    C674X_0: GEL Output: DEV_INFO_03 = 0x00000035
    C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
    C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6128884-7-58-18
    C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,13770
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
    C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
    C674X_0: GEL Output: DEV_INFO_21 = 0x3830306B
    C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_24 = 0x0701203A
    C674X_0: GEL Output: DEV_INFO_25 = 0x005D84F4
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
    C674X_0: GEL Output: DEV_INFO_26 = 0x6B940005
    C674X_0: GEL Output:

    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | BOOTROM Info |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: ROM ID: d800k008
    C674X_0: GEL Output: Silicon Revision 2.1
    C674X_0: GEL Output: Boot pins: 16
    C674X_0: GEL Output: Boot Mode: NAND 16
    C674X_0: GEL Output:
    ROM Status Code: 0x000000FF
    Description:C674X_0: GEL Output: Error code not recognized
    C674X_0: GEL Output:
    Program Counter (PC) = 0xC405F674
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | Clock Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLLs configured to utilize crystal.
    C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    C674X_0: GEL Output:
    C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
    C674X_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
    C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
    C674X_0: GEL Output: and then reload.
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PLL0 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLL0_SYSCLK1 = 456 MHz
    C674X_0: GEL Output: PLL0_SYSCLK2 = 228 MHz
    C674X_0: GEL Output: PLL0_SYSCLK3 = 228 MHz
    C674X_0: GEL Output: PLL0_SYSCLK4 = 114 MHz
    C674X_0: GEL Output: PLL0_SYSCLK5 = 152 MHz
    C674X_0: GEL Output: PLL0_SYSCLK6 = 456 MHz
    C674X_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PLL1 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
    C674X_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
    C674X_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PSC0 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output:
    C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3
    C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3
    C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
    C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
    C674X_0: GEL Output: Module 4: SPI 0 STATE = 3
    C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 0
    C674X_0: GEL Output: Module 6: AINTC STATE = 3
    C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
    C674X_0: GEL Output: Module 9: UART 0 STATE = 3
    C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
    C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
    C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
    C674X_0: GEL Output: Module 13: PRUSS STATE = 0
    C674X_0: GEL Output: Module 14: ARM STATE = 3
    C674X_0: GEL Output: Module 15: DSP STATE = 3
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: | PSC1 Information |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output:
    C674X_0: GEL Output: Module 0: EDMA3CC (1) STATE = 3
    C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 3
    C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 3
    C674X_0: GEL Output: Module 3: GPIO STATE = 3
    C674X_0: GEL Output: Module 4: UHPI STATE = 0
    C674X_0: GEL Output: Module 5: EMAC STATE = 0
    C674X_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3
    C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3
    C674X_0: GEL Output: Module 8: SATA STATE = 0
    C674X_0: GEL Output: Module 9: VPIF STATE = 0
    C674X_0: GEL Output: Module 10: SPI 1 STATE = 0
    C674X_0: GEL Output: Module 11: I2C 1 STATE = 0
    C674X_0: GEL Output: Module 12: UART 1 STATE = 3
    C674X_0: GEL Output: Module 13: UART 2 STATE = 3
    C674X_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
    C674X_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
    C674X_0: GEL Output: Module 16: LCDC STATE = 0
    C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
    C674X_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
    C674X_0: GEL Output: Module 19: UPP STATE = 0
    C674X_0: GEL Output: Module 20: eCAP (all) STATE = 0
    C674X_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
    C674X_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
    C674X_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
    C674X_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
    C674X_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
    C674X_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
    C674X_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
    C674X_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
    C674X_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3


    Non Working One:

    ARM9_0: GEL Output:
    ---------------------------------------------
    ARM9_0: GEL Output: | Device Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_02 = 0x00000010
    ARM9_0: GEL Output: DEV_INFO_03 = 0x00000035
    ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6128884-7-58-18
    ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,13770
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003
    ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_20 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_21 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864
    ARM9_0: GEL Output: DEV_INFO_23 = 0x3830306B
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_24 = 0x0701203A
    ARM9_0: GEL Output: DEV_INFO_25 = 0x005D84F4
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_26 = 0x6B940005
    ARM9_0: GEL Output:

    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | BOOTROM Info |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: ROM ID: d800k008
    ARM9_0: GEL Output: Silicon Revision 2.1
    ARM9_0: GEL Output: Boot pins: 16
    ARM9_0: GEL Output: Boot Mode: NAND 16
    ARM9_0: GEL Output:
    ROM Status Code: 0x00000000
    Description:ARM9_0: GEL Output: No error
    ARM9_0: GEL Output:
    Program Counter (PC) = 0x80005E3C
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | Clock Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLLs configured to utilize crystal.
    ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
    ARM9_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
    ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,
    ARM9_0: GEL Output: and then reload.
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL0_SYSCLK1 = 456 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK2 = 228 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK3 = 228 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK4 = 114 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK5 = 152 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK6 = 456 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC0 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (0) STATE = 0
    ARM9_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0
    ARM9_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
    ARM9_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
    ARM9_0: GEL Output: Module 4: SPI 0 STATE = 0
    ARM9_0: GEL Output: Module 5: MMC/SD 0 STATE = 0
    ARM9_0: GEL Output: Module 6: AINTC STATE = 3
    ARM9_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
    ARM9_0: GEL Output: Module 9: UART 0 STATE = 0
    ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
    ARM9_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
    ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
    ARM9_0: GEL Output: Module 13: PRUSS STATE = 0
    ARM9_0: GEL Output: Module 14: ARM STATE = 3
    ARM9_0: GEL Output: Module 15: DSP STATE = 0
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PSC1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: Module 0: EDMA3CC (1) STATE = 0
    ARM9_0: GEL Output: Module 1: USB0 (2.0) STATE = 3
    ARM9_0: GEL Output: Module 2: USB1 (1.1) STATE = 0
    ARM9_0: GEL Output: Module 3: GPIO STATE = 0
    ARM9_0: GEL Output: Module 4: UHPI STATE = 0
    ARM9_0: GEL Output: Module 5: EMAC STATE = 0
    ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3
    ARM9_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 8: SATA STATE = 0
    ARM9_0: GEL Output: Module 9: VPIF STATE = 0
    ARM9_0: GEL Output: Module 10: SPI 1 STATE = 0
    ARM9_0: GEL Output: Module 11: I2C 1 STATE = 0
    ARM9_0: GEL Output: Module 12: UART 1 STATE = 0
    ARM9_0: GEL Output: Module 13: UART 2 STATE = 3
    ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
    ARM9_0: GEL Output: Module 16: LCDC STATE = 0
    ARM9_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
    ARM9_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
    ARM9_0: GEL Output: Module 19: UPP STATE = 0
    ARM9_0: GEL Output: Module 20: eCAP (all) STATE = 0
    ARM9_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
    ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
    ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
    ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
    ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
    ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
    ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
    ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
    ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3
  • 0 in reply to Senthil Kumar11061
    TI__Guru** 114410 points

    This appears to be the correct log from the device booting at 456 Mhz.

    Senthil Kumar11061 said:
    ARM9_0: GEL Output:
    ROM Status Code: 0x00000000
    Description:ARM9_0: GEL Output: No error
    ARM9_0: GEL Output:
    Program Counter (PC) = 0x80005E3C

    As you can see in the non-working case, the ROM bootloader appears to have booted  without any errors and the core is executing code in DDR memory so the code seems to have hung in your application code rather than the bootloader. At this point, you can load the symbols from the application to see where the device is at or look at the .map file to see what symbol is at location 

    Regards,

    Rahul