RTOS: SysBios/NoSysBios - EMIFA/EMIFB Speed differences

Tom Heckel

Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hello together,

// OMAPL137BZKB3

I'm using SysBios (just the BIOS module) for my project and I am running my firmware wihtin the L2 RAM (256k).
After some years my project has become quite big and it will not fit into the L2 RAM anymore.
So since I'm not using tasks or anything special from the SysBios, my solution was to simply remove the SysBios from my project (gave me about 25k space back).
Everything worked fine so far, but I figured out that for some reason the memory accesses seems to be faster with SysBios.

I made two test projects with same code to figure that out (SysBios/NoSysBios):
(I tested this by toggleing pins and read them with an oszi)

void main(void)
{
  // INIT STUFF (SAME FOR SysBios/NoSysBios)
  // PLL 300MHz
  // SDRAM 16 MB (0xC7000000 - 0xC8000000) -> using same EMIFB configuration
  // ...
  
	Uint8 * pSdram;

  // just using a SDRAM(EMIFB) address
	pSdram = (Uint8*)0xC7FFFB00;
  
  // Writing on EMIFB
  // SysBios   -> 54ns
  // NoSysBios -> 54ns
	*pSdram = 0;      
  
  // Reading/Writing on EMIFB
  // SysBios   -> 54ns
  // NoSysBios -> 54ns
	*pSdram ^= *pSdram;
  
  // Reading from EMIFB/Writing on EMIFA
  // SysBios   -> 67ns
  // NoSysBios -> 242ns // ???
	*((volatile Uint8*)0x60000301) = *pSdram;
  
  // Writing on EMIFA
  // SysBios   -> 54ns
  // NoSysBios -> 54ns
	*((volatile Uint8*)0x60000301) = 0; 
  
  // Reading/Writing on EMIFA
  // SysBios   -> 320ns
  // NoSysBios -> 307ns
	*((volatile Uint8*)0x60000301) ^= *((volatile Uint8*)0x60000301);
}

When getting the register dump from CCS for both projects the configuration is the same.
Also the assembler code of this main.obj looks exactly the same.

Does anyone have an idea what this causes?

Best Regards, Tom

over 6 years ago

0 ToddMullanix over 6 years ago

TI__Guru* 96960 points

Tom,

Are you enabling cache on the device? Is the placement of the code the same for both projects? Which core are you seeing this on?

Todd

0 Tom Heckel over 6 years ago in reply to ToddMullanix

Intellectual 515 points

Hi Todd,

thanks for the reply.

I'm running this firmware on DSP (OMAPL137) within L2 Ram.

The cache control registers of L1/L2 are exactly the same for both projects (got them by debugging with CCS). But I did not force caching by myself.

What do you mean by placement? The code for both projects are the same, as are the asm files.

Best Regards, Tom

0 ToddMullanix over 6 years ago in reply to Tom Heckel

TI__Guru* 96960 points

Tom Heckel said:
What do you mean by placement? The code for both projects are the same, as are the asm files.

Is main() at the exact same location in memory for both projects?

SYS/BIOS does some setup before main(). It could be populating the cache before main().

0 Tom Heckel over 6 years ago in reply to ToddMullanix

Intellectual 515 points

Hi Todd,

sorry for the misunderstanding. No the main.obj is at a different location in the map file of both projects.
Thats what I thougt too. But since the register values are the same I coulnd't really found sense in that.

Best Regards, Tom

0 ToddMullanix over 6 years ago in reply to Tom Heckel

TI__Guru* 96960 points

Can you confirm the cache MAR bits are exactly the same?

0 Tom Heckel over 6 years ago in reply to ToddMullanix

Intellectual 515 points

Hi Todd,

you are right. Unfortunately, the register dump I exported with CCS did not contain the cache registers. When I first thought of a caching I just logged out the control registers of the L1/L2 caches, but not the MAR registers.

With SysBios the MAR199 Bit is set to 1. THis register represents my SDRAM region. So setting this register to 1 solved my problem.

Thanks for your support.

Best Regards, Tom

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RTOS: SysBios/NoSysBios - EMIFA/EMIFB Speed differences