• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 101 subscribers
  • Views 710 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAP-L138: Please clarify: L2 cache has two addresses in data sheet i.e. @0x0080 0000 and @0x1180 0000

Ashish Maheshwari
Intellectual 660 points
Part Number: OMAP-L138
Other Parts Discussed in Thread: OMAPL138

Dear All,

Please clarify the doubt about  L2 cache memory allocation

In Omapl138 data sheet section 3.5 table 3.4 "Top Level Memory Map" page number 22 it says that "0x0080 0000 0x0083 FFFF 256K DSP L2 RAM" and on same table at page number 24 it says "0x1180 0000 0x1183 FFFF 256K DSP L2 RAM"

http://www.ti.com/lit/ds/symlink/omap-l138.pdf 

My questions are below

a) What is the difference between these two locations of same L2 cache

b) Which location to use or we can use both the locations (i.e. 256 k at location 0x0080 0000 and 256 k at location 0x1180 0000)

Regards

Ashish

  • 0
    TI__Guru**** 161600 points
    Hi,

    The first memory addresses on page 22:
    0x0080 0000 0x0083 FFFF 256K DSP L2 RAM ===> this is the address viewed from the DSP. In this case it is assumed that you access the DSP L2RAM directly from within the DSP.

    The other location
    0x1180 0000 0x1183 FFFF 256K DSP L2 RAM
    is a top level view of the DSP L2 RAM accessed by the ARM & the ther master peripherals via the system interconnect through the DSP SDMA port.

    NOTE that you should also refer to the TRM of the device, see Section 5.3 DSP Memories:
    "5.3 DSP Memories
    The DSP internal memories are accessible by the ARM and other master peripherals (as dictated by the
    connectivity matrix) via the system interconnect through the DSP SDMA port.
    The DSP internal memory consists of L1P, L1D, and L2. The DSP internal memory configuration is:
    • L1P memory includes 32 KB of RAM. The DSP program memory controller (PMC) allows you to configure part or all of the L1P RAM as normal program RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB cache.
    • L1D memory includes 32 KB of RAM. The DSP data memory controller (DMC) allows you to configure part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB cache.
    • L2 memory includes 256 KB of RAM. The DSP unified memory controller (UMC) allows you to configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, or 256 KB of the 256 KB of RAM. The default configuration is 256 KB normal RAM.
    • L2 memory also includes 1024 KB of ROM."

    Best Regards,
    Yordan