RTOS: What should be the cache-able option for shared memory for IPC

Tool/software: TI-RTOS

Hi there, I have installed IPC 3.46.00.02 and have run the ex02_messageq example on OMAPL138 and with Linux on ARM.

I don't understand the cache option added in the DSP.cfg file :

var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
/* Set 0xc4000000 -> 0xc4ffffff to be non-cached for shared memory IPC */
Cache.MAR192_223 = 0x00000010;

I guess, the comment is wrong to start with. Here we are disabling the 0xc3000000 rather than 0xc4000000. 

Could you explain what is the idea about this cache option? should IPC memory not be cache-able ? 

Attached the full dsp.cfg file for your reference.

Thanks.2337.Dsp.cfg

21 Replies

  • Hi there,
    In the ex02 example the configuration for messageQ uses HeapBuf and then register it to heapID 0. Is there a way to add that this heap is cache enabled?

    Lines from dsp.cfg file:
    /* create a heap for MessageQ messages */
    var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
    var params = new HeapBuf.Params;
    params.align = 8;
    params.blockSize = 512;
    params.numBlocks = 256;
    var msgHeap = HeapBuf.create(params);

    var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
    MessageQ.registerHeapMeta(msgHeap, 0);
  • In reply to Mitesh Hiran:

    Hi there,

    is there any way to run this ex02 example with Cache enabled for the heap memory.

  • In reply to Mitesh Hiran:

    Hi,

    I've notified the RTOS team. Their feedback will be posted directly here.

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • Check the MAR bit description here:
    www.ti.com/.../sprufk5a.pdf

    MAR192 corresponds to bit 0 and MAR196 corresponds to bit 4 which is set to 1 in the configuration.

    Interpretation of that setting can be found in the SYBIOS documentation:
    software-dl.ti.com/.../Cache.html

    If you don`t prefer using the .cfg for this setting then you can use the APIs provided here:
    software-dl.ti.com/.../Cache.html

    Regards,
    Rahul

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  • In reply to Rahul Prabhu:

    Hi Rahul,

    so the comment in the ex02 example configuration is wrong. 

    It says 

    /* Set 0xc4000000 -> 0xc4ffffff to be non-cached for shared memory IPC */
    //Cache.MAR192_223 = 0x00000010;

    However, its enabled 0xc4000000 -> 0xc4ffffff and the rest is disabled.

    How can use the ex02 example with following settings:

    Cache.MAR192_223 = 0x00000018;

    The entry point of the design is 0xc3000000

  • In reply to Mitesh Hiran:

    Hi Mitesh,

    I think you are correct, Cache.MAR192_223 = 0x00000010 sets 0xc4000000 -> 0xc4fffff to be cacheable. I will confirm this with the team.

    Cache.MAR192_223 = 0x00000018 will set 0xc3000000 -> 0xc4ffffff to be cached.

    You can find more information on cache configuration in the cdoc for the ti.sysbios.family.c64p.Cache module. The cdoc can be found in the \bios_6_46_05_55\docs\cdoc\ti\sysbios\family\c64p\Cache.html directory.

    You can also take a look at the following code snippet for reference:

    /* configure external memory cache property
    *
    * C000_0000 - C7FF_FFFF 800_0000 ( 128 MB) Cache.MAR192_223
    * ----------------------------------------------------------------------------
    * C000_0000 - C1FF_FFFF 200_0000 ( 32 MB) -------- don't care
    * C200_0000 - C202_FFFF 3_0000 ( 192 KB) SR_0, SR-1 no-cache MAR194
    * C203_0000 - C2FF_FFFF FD_0000 ( ~15 MB) -------- no-cache MAR194
    * C300_0000 - C37F_FFFF 80_0000 ( 8 MB) DSP_PROG cache enable MAR195
    * C380_0000 - C3FF_FFFF 80_0000 ( 8 MB) -------- cache enable MAR195
    * C400_0000 - C7FF_FFFF 400_0000 ( 64 MB) -------- don't care
    */

    Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
    Cache.MAR192_223 = 0x00000008; /* xxxx xxxx xxxx xxxx xxxx xxxx xxxx 10xx */


    Once you have it configured, you can use ROV to check the state of the cache. Take a look at the following thread for more information:

    e2e.ti.com/.../111081


    Hope this helps. Let us know if you have any questions.

    Best,
    Sahin

  • In reply to Sahin Okur:

    Hi Sahin,

    When I run the example with defualt cache settings all seems to work. However, when I change the use cache for the messageQ heap the example ex02 design stops working!!!

    Could you please help me with this.. How can I use the ex02 example with cache enabled. Thanks. 

    DO I need to add cache write back functions? 

  • In reply to Mitesh Hiran:

    Hi there, any update on this issue, please?
    Thanks

  • In reply to Mitesh Hiran:

    Hi there, 

    In my design I would like to use Cache option for the software running on the DSP. Looking at the example for the IPC it looks like the Cache is disabled for IPC communications.

    Is there a way to use Internal On-Chip memory on OMAPL138 address 0x80000000 SharedRam ?

    I have added following code in the configuration file:

    /* Shared Memory base address and length */
    var SHAREDMEM = 0x80001400;
    var SHAREDMEMSIZE = 0x00020000;

    /*
    * Need to define the shared region. The IPC modules use this
    * to make portable pointers. All processors need to add this
    * call with their base address of the shared memory region.
    * If the processor cannot access the memory, do not add it.
    */
    var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
    SharedRegion.setEntryMeta(0,
    { base: SHAREDMEM,
    len: SHAREDMEMSIZE,
    ownerProcId: 0,
    isValid: true,
    createHeap: true,
    cacheEnable: true,
    name: "SharedMem",
    });

    var HeapMemMP = xdc.useModule('ti.sdo.ipc.heaps.HeapMemMP');
    var paramsMP = new HeapMemMP.Params;
    paramsMP.name = "shr";
    paramsMP.regionId = 0;
    paramsMP.sharedAddr = SHAREDMEM;
    paramsMP.sharedBufSize = SHAREDMEMSIZE;
    var msgHeap1 = HeapMemMP.create(paramsMP);

     

    How can use this buffer as the Heap for MessageQ?

    Thanks.

  • In reply to Mitesh Hiran:

    Hi Mitesh,

    Sorry for the delayed response. In your SharedRegion configuration, you have createHeap set to "true", which instructs IPC to automatically create a HeapMemMP instance that is the size of the entire shared region. With this configuration, you do not need to create another HeapMemMP instance as you do in your cfg file.

    If you want to create a HeapMemMP instance using just a subset of the shared region, then set createHeap to "false" and create the HeapMemMP instance as you do. Just note, the size of the HeapMemMP needs to be less than the SharedRegion.

    Also, any IPC instance created within the SharedRegion will inherit the cache settings of the SharedRegion. So since you set cacheEnable to "true", the HeapMemMP instance created will also be cache-enabled. (refer to http://www.ti.com/lit/ug/sprugo6e/sprugo6e.pdf#page=62)

    I hope this helps. Please let us know if you have any other questions.

    Best,
    Sahin