PROCESSOR-SDK-OMAPL138: OMAPL138 underrun error in EDMA data transmition to mcasp XBUF.

Hello!

I'am using OMAPL138-C6748 Processor to finish the data transmition with EDMA by Peripheral configuration bus. MCASP finishes the data transmition with tlv320aic29 as the master device, and the EDMA uses the AB-synchronized transmition. The system runs normally at the beginning, but as the time goes on(maybe about two days later), the system runs abnormally with a underrun error in XSTAT register(the XUNDRN bit = 1, while the XDATA bit =1, too). At this time, EDMA doesn't transfer data anymore, and the CCNT register stays with the number neither the maximum count nor zero. And the receive sections of MCASP still works normally. The detial configuration of MCASP is listed as follows: Can  anybody help?

 // reset mcasp.

mcasp0regs->GBLCTL = 0;

// configure receive registers.

mcasp0regs->RMASK           = 0x0000FFFF;

mcasp0regs->RFMT              = 0x00018078;

mcasp0regs->AFSRCTL       = 0x00000102;

mcasp0regs->ACLKRCTL    = 0x00000029;

mcasp0regs->AHCLKRCTL = 0x00008004;

mcasp0regs->RTDM              = 0x00000001;

mcasp0regs->RCLKCHK      = 0x00FF0008;

mcasp0regs->REVTCTL       = 0x00000000;

// configure transmit registers.

mcasp0regs->XMASK           = 0x0000FFFF;  

mcasp0regs->XFMT              = 0x0001807C; //1-bit delay;MSB first;Slot size is 16 bits;Rotate right by 16 bit positions.

mcasp0regs->AFSXCTL       = 0x00000102; //2-slot TDM(I2S mode),Single bit,Internally-generated transmit frame sync, rising edge on transmit frame sync(AFSX)indicates the beginning of a frame

mcasp0regs->ACLKXCTL    = 0x00000029; //Rising edge,Single bit,Internal transmit clock source from output of programmable bit clock divider(CLKXDIV=0x09)

mcasp0regs->AHCLKXCTL = 0x00008004; //Internal transmit high-frequency clock source(HCLKXDIV=0x04)

mcasp0regs->XTDM              = 0x00000003; //Slot 0,1

mcasp0regs->RCLKCHK     = 0x00FF0008;

mcasp0regs->XEVTCTL       = 0x00000000; //Transmit data DMA request is enabled.

// config serializers (14= xmit, 15= rcv).

mcasp0regs->SRCTL14 = 0x00000001;

mcasp0regs->SRCTL15 = 0x00000002;

// config pin function and direction.

mcasp0regs->PFUNC  = 0;

mcasp0regs->PDIR   = 0x1C004000;

mcasp0regs->DITCTL = 0x00000000;

mcasp0regs->DLBCTL = 0x00000000;

mcasp0regs->AMUTE  = 0x00000000;

while ((0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_XHCLKRST_MASK)) || (0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_RHCLKRST_MASK)))

{

mcasp0regs->GBLCTL |= ((CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE<<CSL_MCASP_GBLCTL_XHCLKRST_SHIFT) | (CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE<<CSL_MCASP_GBLCTL_RHCLKRST_SHIFT));

}

while ((0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_XCLKRST_MASK)) || (0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_RCLKRST_MASK)))

{

mcasp0regs->GBLCTL |= ((CSL_MCASP_GBLCTL_XCLKRST_ACTIVE<<CSL_MCASP_GBLCTL_XCLKRST_SHIFT) | (CSL_MCASP_GBLCTL_RCLKRST_ACTIVE<<CSL_MCASP_GBLCTL_RCLKRST_SHIFT));

}

//enable the transmit and/ or receive interrupt

IER |= 0x4000;

edma_mcasp0rx_set();

edma_mcasp0tx_set();

//clear the respective transmitter and receiver status registers

mcasp0regs->RSTAT=0x0000FFFF;

task_delay();

mcasp0regs->XSTAT=0x0000FFFF;

//Take the respective serializers out of reset

while ((0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_XSRCLR_MASK)) || (0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_RSRCLR_MASK)))

{

        mcasp0regs->GBLCTL |= ((CSL_MCASP_GBLCTL_XSRCLR_ACTIVE<<CSL_MCASP_GBLCTL_XSRCLR_SHIFT) | (CSL_MCASP_GBLCTL_RSRCLR_ACTIVE<<CSL_MCASP_GBLCTL_RSRCLR_SHIFT));

}

while ((0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_XSMRST_MASK)) || (0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_RSMRST_MASK)))

 {

mcasp0regs->GBLCTL |= ((CSL_MCASP_GBLCTL_XSMRST_ACTIVE<<CSL_MCASP_GBLCTL_XSMRST_SHIFT) | (CSL_MCASP_GBLCTL_RSMRST_ACTIVE<<CSL_MCASP_GBLCTL_RSMRST_SHIFT));

}

//Take the respective frame sync generator(s) out of reset

while ((0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_XFRST_MASK)) || (0 == (mcasp0regs->GBLCTL & CSL_MCASP_GBLCTL_RFRST_MASK)))

{

mcasp0regs->GBLCTL |= ((CSL_MCASP_GBLCTL_XFRST_ACTIVE<<CSL_MCASP_GBLCTL_XFRST_SHIFT) | (CSL_MCASP_GBLCTL_RFRST_ACTIVE<<CSL_MCASP_GBLCTL_RFRST_SHIFT));

}