OMAP-L138: OMAP-L137 : Calculation of HW Interrupt overhead

Hi,

I've notified the design team. They will post their feedback directly here.

Best Regards,
Yordan

Hello Lorraine,

Timing benchmarks can be found in the BIOS install directory under packages/ti/sysbios/benchmarks/doc-files. The OMAP-L137 DSP (C6748) benchmarks are listed in the file "TI_C674_ti_platforms_evmTI814X_time.html." It lists 227 cycles for interrupt latency, 113 cycles for the hwi prolog, 138 cycles for the hwi epilog, and 246 cycles for the hwi dispatcher.

I believe you can reduce these numbers by using Hwi_plug, which basically allows for hardware interrupts without the SYS/BIOS overhead. Take a look at this thread for more info:
e2e.ti.com/.../372449

I think using the OMAP-L138's uPP would result in less overhead since the uPP has an internal DMA, but I need to check with the hardware team and get back to you.

Which ADC are you using?

Regards,
Sahin

Hi Lorraine,
Yes please clarify what ADC;s you are using.

In general uPP maybe better suited for such ADCs , but I have to admit that we have limited eco system in term of software in the Processor SDK and our ability to hook up an ADC directly to the EVM (OMAPL138 LCDK), that makes it harder for customers to evaluate performance in proto /development stage, so you need to be careful about that.

We do have strong 3P who have hardware and software references around this
www.criticallink.com/.../

So please keep that in mind.

On OMAPL137 the parallel interface to use is the EMIFA .

This is assuming that the ADCs you are using cannot be used with some of the standard serial ports like SPI etc (likely if the bandwidth requirement is higher).

Regards
Mukul

Thanks for your prompt and detailed responses.

It looks like I'm going to have to work with the existing HW at the moment where the ADC is connected into GPIO pins. If/when I get a chance to re-spin the HW, I am sure I'll be back with lots of extra questions regarding EMIF, UPP, ADCs etc

In the meantime, I need to work out the limitations on the existing HW.

Can you please look at the calculation below and let me know if I am using the supplied numbers correctly.

I have a 300MHz L137. My ADC is working at a sampling frequency of 50kHz, so I calculate that I have 6000 L137 clock cycles between hardware interrupts.

If I estimate that 'user defined' part of my HWI handler will require 100 cycles, then I can estimate that the total processing cycles to handle the HWI will be
113(dispatcher prolog) + 100(user defined) + 138(dispatcher epilogue) = 351 cycles.
This would allow me to estimate that handling the HWI will require 351/6000 = 5.85% of my processing power.

If I want the HWI to post a semaphore to indicate when a buffer has been filled and is ready for processing, then I need to increase my estimate by 47/160/220(?) cycles .

I have assumed that the interrupt latency is not a factor in this calculation as the L137 will be doing other useful work during that time.

Does that all make sense ??

with thanks and regards

Lorraine