OMAP-L138: 456MHz problem

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BR
Tsvetolin Shulev

Hello,

Are you running Linux on the ARM? Can you please share the PLL settings you used with AISGen?

hello,

I am not using Linux. Both firmwares are no-OS.

The PLL settings are the same as GEL file for 456MHz, that works perfectly on JTAG.

Thanks,

Gloria

Rahul,

Thanks fou your attention.

The core- voltage is ok (1.3v), It is working in the CCS with the associated gel file (for 456Mhz).

When I configure AIS for 456MHz, It works as 300MHz.456MHz.cfg

I have already checked the clocking spreadsheet and it is ok.

The AISGen configuration is attached

Regards,

Glória

 

Gloria,

Thanks for sharing the configuration. Based on the AIS config, I can confirm that the PLL0 is being set correctly to 456 MHz. The question now remains, is what software is re-configuring the clocks and setting them to 300 Mhz. Do you have any PLL configuration in your secondary bootloader or application code that may be re configuring the clocks to 300 MHz. could you indicate how you determined that the core is running at 300 MHz post boot?

I am assuming from your AISGen configuration that you are using NAND flash boot mode and flashing the NAND using UART, is that correct? Or are you trying to boot the AISGen image over UART bootmode?

Regards,
Rahul

Rahul,

I do not have any other configuration of the PLL on the firmwares.
It is really wierd, but I can confirm that it is on 300MHz.
I have the same performance of when I test under ccs with gel on 300Mhz.
I confirmed it using OBSCLK.
You are right: I am using NAND FLASH boot mode and flashing the NAND using UART. The process is ok.

Regards,
Gloria

gloria,

Did you get a chance to run the Debug GEL file and provide us the output. Also, can you provide the full part number so I can confirm that the device variant you have is 456 Mhz qualified part.Did you erase the NAND before you re-programmed the NAND ? Was there a 300 Mhz configuration on the NAND before you re-programmed it ?

Regards,
Rahul

Rahul,

Yes, I erased the flash.

It is a 456Mhz qualified part, I can achieve this frequency with JATG and CCS. I just have problems when it is stand-alone.

The part number is: OMAPL138EZWT4

Regards,

Gloria

Hi Gloria
Thanks for the update, i think we really do need the output of the debug gel file, as Rahul mentioned in his last post
>>Did you get a chance to run the Debug GEL file and provide us the output.

We are missing something here and the debug gel file output may help us diagnose this further.

Regards
Mukul

Mukul and Rahul,

This is the outpu of the GEL file:

C674X_0: Output: Target Connected.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Cleared.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Setup Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: KICK Unlocked.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PSC Enable Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PLL0 init done for Core:456MHz, EMIF:24MHz
C674X_0: Output: mDDR initialization is in progress....
C674X_0: Output: PLL1 init done for DDR:150MHz
C674X_0: Output: Using mDDR settings
C674X_0: Output: mDDR init for 150 MHz is done
C674X_0: Output: ---------------------------------------------


Regards,
Gloria

Sorry, we should've been more clear , when we said output of debug gel file

please see the wiki on debug gel file here
processors.wiki.ti.com/.../OMAP-L1x_Debug_Gel_Files
Once you have booted up via flash, please connect to device via JTAG, and run the gel file from this wiki, this gives us the various PSC/PLL , boot program counter settings.

Mukul,

This is the output:

C674X_0: Output: Target Connected.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Cleared.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Setup Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: KICK Unlocked.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PSC Enable Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PLL0 init done for Core:456MHz, EMIF:24MHz
C674X_0: Output: mDDR initialization is in progress....
C674X_0: Output: PLL1 init done for DDR:150MHz
C674X_0: Output: Using mDDR settings
C674X_0: Output: mDDR init for 150 MHz is done
C674X_0: Output: ---------------------------------------------
C674X_0: GEL Output:
---------------------------------------------
C674X_0: GEL Output: | Device Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x00000010
C674X_0: GEL Output: DEV_INFO_03 = 0x00000035
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-4144391-10-24-6
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,10694
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3830306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x0A006018
C674X_0: GEL Output: DEV_INFO_25 = 0x003F3D07
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x538C0005
C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | BOOTROM Info |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k008
C674X_0: GEL Output: Silicon Revision 2.1
C674X_0: GEL Output: Boot pins: 16
C674X_0: GEL Output: Boot Mode: NAND 16
C674X_0: GEL Output:
ROM Status Code: 0x00000001
Description:C674X_0: GEL Output: DSP was put to sleep
C674X_0: GEL Output:
Program Counter (PC) = 0x80002770
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | Clock Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize crystal.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PLL0 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_SYSCLK1 = 456 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 228 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 24 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 114 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 152 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 456 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 76 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PLL1 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PSC0 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3
C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3
C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 3
C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
C674X_0: GEL Output: Module 4: SPI 0 STATE = 3
C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 3
C674X_0: GEL Output: Module 6: AINTC STATE = 3
C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
C674X_0: GEL Output: Module 9: UART 0 STATE = 3
C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
C674X_0: GEL Output: Module 13: PRUSS STATE = 0
C674X_0: GEL Output: Module 14: ARM STATE = 3
C674X_0: GEL Output: Module 15: DSP STATE = 3
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PSC1 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0: EDMA3CC (1) STATE = 3
C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 3
C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 3
C674X_0: GEL Output: Module 3: GPIO STATE = 3
C674X_0: GEL Output: Module 4: UHPI STATE = 3
C674X_0: GEL Output: Module 5: EMAC STATE = 3
C674X_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3
C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3
C674X_0: GEL Output: Module 8: SATA STATE = 3
C674X_0: GEL Output: Module 9: VPIF STATE = 3
C674X_0: GEL Output: Module 10: SPI 1 STATE = 3
C674X_0: GEL Output: Module 11: I2C 1 STATE = 3
C674X_0: GEL Output: Module 12: UART 1 STATE = 3
C674X_0: GEL Output: Module 13: UART 2 STATE = 3
C674X_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 3
C674X_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 3
C674X_0: GEL Output: Module 16: LCDC STATE = 3
C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 3
C674X_0: GEL Output: Module 18: MMC/SD 1 STATE = 3
C674X_0: GEL Output: Module 19: UPP STATE = 3
C674X_0: GEL Output: Module 20: eCAP (all) STATE = 3
C674X_0: GEL Output: Module 21: EDMA3 TC2 STATE = 3
C674X_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
C674X_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
C674X_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
C674X_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
C674X_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
C674X_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
C674X_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
C674X_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

Regards,

Gloria

Hi Gloria

As per the output of this debug gel file , the device IS running at 456 MHz
---
C674X_0: GEL Output: PLL0_SYSCLK1 = 456 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 228 MHz
--

So follow up questions for you
1) We may need to make sure that you are running the debug gel file correctly. My assumption is that the way you run and collect this output is , boot the device as you would in your failing case (UART download with the AIS the firmware works as 300MHz.). Connect to JTAG/CCS , ensure that on target connect any default gel file is not running to configure the PLL at 456 MHz - load the debug gel file and then - Go to Scripts -> Diagnostics -> Run All. The key thing is to capture the PLL registers for your failing condition.

2) If you are already doing the above, and output is what you shared, then I believe the device is running at 456 MHz and we need to verify your verification mechanism of why you think it is running at 300 MHz needs to be further examined/understood - so please share the details or capture of the obsclk output etc.

Regards
Mukul