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OMAP-L138: Please clarify the settings between boot loader program and gel file to boot from NAND flash

Part Number: OMAP-L138
Other Parts Discussed in Thread: OMAPL138

Dear Team,

I am using TI’s TMDSLCDK OMAP-L138 evaluation board. In that I want to load my application (boot.ais and program.bin) in NAND flash so that program will boot from NAND to run independently after reset at 300 MHz processor speed and 150 MHz DDR2.

So I checked the settings of PLL0, PLL1 and DDR2 defined in the OMAP-L138 gel file and compare it with the NAND boot loader program (comes with the OMAPL138_StarterWare_1_10_04_01) and found the following differences in PLL0 Div3 and DDR2 SDCR

 

PLL0

 

 

OMAP-L138_LCDK.gel file

NAND Bootloader

 

 

 

Clock src

0

0

Multiplier

24

24

Postdiv

1

1

 

Prediv

Not given

0

Plldiv1

0

0

Plldiv3

11

2

Why there is a change and which setting will I put in bootloader program

Plldiv7

5

5

 

PLL1

 

 

OMAP-L138_LCDK.gel file

NAND Bootloader

 

 

 

Multiplier

24

24

Postdiv

1

1

Plldiv1

0

0

Plldiv2

1

1

Plldiv3

2

2

 

DDR2

 

 

OMAP-L138_LCDK.gel file

NAND Boot loader

 

 

 

SDCR

0x00134832

0x0013C832

Change: TIMUNLOCK

1SET

Timing unlock. Controls the write permission settings for the SDRAM Timing 1 Register and SDRAM Timing 2 Register

SDRCR

0x00000492

0x00000492

SDTMR1

0x264A3209

0x264A3209

SDTMR2

0x3C14C722

0x3C14C722

About SDCR change:

 In boot loader program

In DDR2 configuration function “DDRInit” in bl_platform.c of NAND boot loader program, at line number 620 message is that it will clear “timing unlock” and the value of “DDR2_MDDR_SDCR_BOOTUNLOCK” is

#define DDR2_MDDR_SDCR_BOOTUNLOCK (0x00800000u)

 

/* CLEAR TIMINGUNLOCK */

   HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) &= ~DDR2_MDDR_SDCR_BOOTUNLOCK;

 

In Gel file setting

       In DDR2 configuration function “DEVICE_DDRConfig”

   EMIFDDR_SDCR   &= ~0x00008000; // Clear TIMUNLOCK

 

Pkease suggest us which settings we need to put in boot loader program to boot our application from NAND flash

 

Regards,

Ashish

  • Hi,

    Just wanted to let you know this has been forwarded to the RTOS team. They will post their feedback directly here.

    Best REgards,
    Yordan
  • Ashish,

    The device clocking of different modules is a subjective decision based on the usecase of the end application. As long as the clocks meet the SOC datasheet specs and in line with the external devices that are interface with OMAPL138. Due to different ways and values of these clocks, we provide a clocking spreadsheet that allows users to set the clocks and view the resulting impact of these settings to different modules:

    processors.wiki.ti.com/.../AM18xx

    The PLL0 DIV3 is one of the possible inputs(CFGCHIP3[EMA_CLKSRC]) to EMIFA if you look at the PLL clock tree in the TRM.

    If you set the divider to 2 (Divider is 3) then the PLL0_SYSCLK3 is set to 75 Mhz which is within the 100 Mhz which is maximum setting for EMIF (check data manual timing spec for EMIFA) which is optimized setting from a boot perspective. The GEL sets up the divider to 11 so SYSCLK is set to 25 MHz which is slow to enable users to debug.

    Here is my read of the DDR SDCR settings, if you look at the GEL file, the TIMUNLOCK bit is set and then cleared in the DDR initialization settings which means that the init sequence required users to unlock the bit configure the timing settings and lock the bit back so rogue software doesn`t change these settings. In a GEL where you run the sequence, you have the option of setting the bit and then clearing it but for the bootROM, the users needs to instruct the ROM to unlock the bit and I suspect that the ROM is then not locking it down. From system reliability perspective, I would recommend that you clear that bit as part of your application initialization but when providing this setting to ROM, you need to allow it to unlock the timing configurations so the DDR timing settings can be applied.

    Hope this clarifies the two settings and provides you enough information to choose the setting required for your application.

    Regards,
    Rahul
  • Rahul,
    Thanks for your reply,
    Presently i am doing some different work and i will get back to you when i will again work on this

    Regards,
    Ashish