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OMAP-L138: EDMA Chaining issue in OMAP

Part Number: OMAP-L138

Hi,

I am currently using OMAP-L138 processor. I have been working with C6748 processor in which I have implemented a DMA chaining which was initiated by a synchronous signal at 256 kHz.

1.The synchronous input chained a DMA event to a transfer 2. (TCCHEN enabled) .

2. Moves a character from an array to a single variable, and is chained to SPI event. (ITCHEN and TCCHEN enabled).

3. The SPI event then transmits the 8 bit data and is chained to transfer 2. ( ITCHEN enabled ) .

The process was working well in C6748 processor in which a 40 bit data is transmitted after the each synchronous event.

When I migrated to OMAP with the same project, The 40bits SPI transfer is not happening in alternate synchronous cycles.

What could be the issue ?

i) Non OS environment using Code Composer Studio and JTAG interface.

ii) ARM part is not programmed.

Thank you in advance for any help you can provide.

  • Hi,

    In OMAP, Now I have disabled the chaining processes.

    Now there is only one EDMA event ( ping pong ) which is synchronous with a 256 kHz input clock to GPIO. (GPIO BANK 1 event).

    In the GPIO event, the EDMA controller need to transmit a constant value through SPI.

    Even now, alternate SPI transfers are not happening.

    I have increased the synchronous signal clock frequency to 445 KHz, and now its working. Below that frequency, SPI transfers are missing in alternate events. But its working perfectly at frequencies above 445 kHz. What could be the issue.

    I am attaching the parameter set below, The EDMA event is enabled on channel 7 (GPIO BANK1)

        EDMA3CCPaRAMEntry paramSet;
        p = (unsigned char *)&paramSet;
        i = 0;
    
        /* Clean-up the contents of structure variable. */
        for (i = 0; i < sizeof(paramSet); i++)
        {
            p[i] = 0;
        }
        paramSet.srcAddr = (unsigned int) &dummy_val11;
    
    
        paramSet.destAddr = (unsigned int) (SOC_SPI_1_REGS + SPI_SPIDAT1);;
    
        /* aCnt holds the number of bytes in an array. */
        paramSet.aCnt = (unsigned short) 1;
    
        /* bCnt holds the number of such arrays to be transferred. */
        paramSet.bCnt = (unsigned short) 1;
    
        /* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred. */
        paramSet.cCnt = (unsigned short) 1;
    
        /*
         ** The srcBidx should be incremented by aCnt number of bytes since the
         ** source used here is  memory.
         */
        paramSet.srcBIdx = (short) 0;
    
        paramSet.destBIdx =(short)0;
    
        /* A sync Transfer Mode is set in OPT.*/
        /* srCIdx and destCIdx set to zero since ASYNC Mode is used. */
        paramSet.srcCIdx = (short) 0;
    
        /* Linking transfers in EDMA3 are not used. */
    
        paramSet.linkAddr = (unsigned short)0x4100;
        paramSet.bCntReload = (unsigned short)0;
    
        paramSet.opt = 0x00000000;
    
        /* Set TCC field in OPT with the tccNum. */
        paramSet.opt |= ((22 << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
    
    
        paramSet.opt |= EDMA3CC_OPT_TCINTEN;
    
        EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 9, &paramSet);
    
    
        EDMA3CCPaRAMEntry paramSet1;
        p = (unsigned char *)&paramSet1;
    
    
        /* Clean-up the contents of structure variable. */
        for (i = 0; i < sizeof(paramSet1); i++)
        {
            p[i] = 0;
        }
        paramSet1.srcAddr = (unsigned int) &dummy_val21;
    
    
        paramSet1.destAddr = (unsigned int) (SOC_SPI_1_REGS + SPI_SPIDAT1);;
    
        /* aCnt holds the number of bytes in an array. */
        paramSet1.aCnt = (unsigned short) 1;
    
        /* bCnt holds the number of such arrays to be transferred. */
        paramSet1.bCnt = (unsigned short) 1;
    
        /* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred. */
        paramSet1.cCnt = (unsigned short)1;
    
        /*
         ** The srcBidx should be incremented by aCnt number of bytes since the
         ** source used here is  memory.
         */
        paramSet1.srcBIdx = (short) 0;
        paramSet1.destBIdx =(short)0;
    
        /* A sync Transfer Mode is set in OPT.*/
        /* srCIdx and destCIdx set to zero since ASYNC Mode is used. */
        paramSet1.srcCIdx = (short) 0;
    
        /* Linking transfers in EDMA3 are not used. */
    
        paramSet1.linkAddr = (unsigned short)0x4120;
    
        paramSet1.bCntReload = (unsigned short)0;
    
        paramSet1.opt = 0x00000000;
    
    
        /* Set TCC field in OPT with the tccNum. */
        paramSet1.opt |= ((22 << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
        paramSet1.opt |= EDMA3CC_OPT_TCINTEN;
    
        EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 8, &paramSet1);
    
        EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 7, &paramSet1);
    }
    
    

    Thank you in advance for any help you can provide.

  • Hi,

    I've notified the sw team. They will post their feedback directly here.

    Best Regards,
    Yordan
  • Hello,

    The Starterware package is no longer supported by TI. Recommendation is to migrate to the latest RTOS Processor SDK:
    www.ti.com/.../PROCESSOR-SDK-OMAPL138
  • Thank You  Sahin Okur,

    Thanks for the information.