I would like to minimise the boot time when using the OMAPL-138
I can find nothing in the documentation regarding when RESET can be de-asserted after power up - other than the voltages must have stabilized and the reset must be low for a minimum of 100ns.
The PMIC used on the LogicPD EVM uses the TPS65070 which releases reset only 400ms after the last supply has stabilized. Are there any other considerations than stable power - clock maybe - that would require a 0.4 sec delay?
Thanks
Steve
Yep, you've got it. Power must be stable and clocks must be stable. There is a diagram in the datasheet, Figure 6-4, that indicates the OSCIN clock input should be stable before the release of reset.
I would also state, that it is important for the boot mode selection pins, described in Section 3.9.11, should be in a stable state before the release of reset. These will determine which mode the device boots in and is selected when reset is deasserted.
Brandon
Hi
Why in the newest omap-l132 datasheet http://www.ti.com/product/omap-l138 http://www.ti.com/product/omap-l132 don't has the Figure 6-4 describe about the timing delay .Can you tell me the in the slva371b.pdf ( http://www.ti.com/lit/an/slva371b/slva371b.pdf ), what is the ” timing delay “ ？