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RVDD on OMAP-L138

Other Parts Discussed in Thread: OMAP-L138, AM1808

Hi,

I am reviewing a board design that uses the OMAP-L138.  The goal is for the board to support both the 375 MHZ and 456 MHz speed grade parts.  

There was another post, http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/90534/314413.aspx#314413, that basically says that the RVDD may be connected to the CVDD supply so long as DVFS is not used.  

Can you clarify this?  For example, if we constrain the minimum core voltage to 1.2 V with DVFS and transition from 300 to 456 Mhz and back such that the supply transisions from 1.2 to 1.3 (and back to 1.2), is this an illegal form of operation?  We would like the option of reducing as much power as needed during known periods of idle time, but would prefer not to add an additional supply for RVDD in order to accomplish this.

Also, this board was intended to be compatible with the AM1808 processor, but the specs for the RVDD pin for that processor are 1.2 or 1.26 volts, with no mention/conditions on the 1.3 volt (456 MHz) operating point.  Does the AM1808 spec for RVDD need to be updated, or are the 456 MHz parts not pin compatible?

Thanks.

-Mike

 

 

 

  • Mike,

    We are updating the datasheets to make this more clear but here are the limitations:

    If you are using a 375 MHz rated device with DVFS, the legal combinations are:

    CVDD = 1.2V; RVDD=1.2V

    CVDD = 1.1V; RVDD=1.2V

    CVDD = 1.0V; RVDD=1.2V

    If you are using a 456 MHz rated device with DVFS, the legal combinations are:

    CVDD = 1.3V; RVDD=1.3V

    CVDD = 1.2V; RVDD=1.3V

     

    CVDD = 1.1V; RVDD=1.3V

    CVDD = 1.0V; RVDD=1.3V

    CVDD should not exceed RVDD, but RVDD also cannot drop below 1.2V. So for the 456 MHz versions, it's usually easiest to leave RVDD at 1.3V

    Regards,

    Clay

  • Clay,

    Sorry to beat this to death.  But does the list above apply for both AM1808 and OMAP-L138, or just OMAP-L138?

    The latest reference design for the OMAP-L138 module from Logic PD does not comply with the above spec (the RVDD pins are only attached to 1.2V) for 456 MHz operation, only 375 MHz operation.  Also, it looks like the reference DVFS design, http://focus.ti.com/lit/an/slva339b/slva339b.pdf, will not work for 456 MHz operation without an additional supply added to support RVDD at 1.3V.

    Is there a reference power supply solution that allows DVFS with a 456 MHz rated part?  Thanks for your help.

    -Mike

  • One further question:

    Is CVDD=1.2 and RVDD=1.2 legal for 456 MHz parts?

    E.g., we can tie CVDD to RVDD and then disable DVFS, but on reset our PMIC defaults CVDD to 1.2 V.  The processor can bumps it up to 1.3V in UBL (or u-Boot or Kernel) before bumping the CPU past 375 MHz, but it's already running at this point.   Is this an issue?  Do we need to alter our PMIC design to start at 1.3 V to support the 456 MHz devices?

    -Mike

     

  • Hi,

    it seems still unclear:

    Is  RVDD = CVDD = 1.2V  legal for 456 MHz rated part operating at fixed frequency less than 375 MHz  without DVFS?

    Thanks,
         Denis

  • If a 456MHz grade device is only going to be used within the boundaries of a 375MHz grade device, it is ok to use the 375MHz grade supply levels.

  • and if i'm using 456Mhz, making RVDD = 1.3V and using core voltage from 1V-1.3V

    does core voltage need to have default value on Wake up ?

    and does there a specific sequence between CVDD and RVDD ?

    thank

    Mor hundert

  • Mor,

    It is always recommended to create a new thread for your queries. Follow up on the old queries may get less attention.

    Yes, the CVDD and RVDD should be at nominal value during start-up. You can refer the section 6.3.1 Power-On Sequence in data manual to understand the power sequence requirement.

    Regards,
    Senthil
  • new thread = new topic. this question should be regarding this topic.
    i'm familiar with the power sequence requirement.
    as indicated in datasheet there is no reference for separated core voltage and RVDD voltage.
    so when i'm splitting RVDD = 1.3V, VCORE = 1.2V (deafult) and changing between 1-1.3V.
    Is there a sequence between RVDD and CVDD ???
    Who should come before CVDD or RVDD ? and if it matters as long as they are before 1.8V and 3.3V ?
  • Mor,

    As mentioned in the section 6.3.1 Power-On Sequence in the dagta manual, CVDD should comes first and then RVDD.

    Regards,
    Senthil