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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » OMAP™ Processors » OMAP-L13x, AM1x and C674x Processors Forum » All Tags » 2X_CLK
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2X_CLK
  • am-1808
  • AM1808
  • ddr2
  • DDR2/mDDR controller
  • omap l138
  • VCLK
Related Posts
  • Forum Post: L138: core VS DDR2/mDDR controller 2X_CLK frequency

    Anonymous Anonymous
    Hi, I would like to ask a question on DDR2/mDDR controller of L138. It has two clock sources 1) VCLK for FIFOs {command, write, read} 2) 2X_CLK, ÷2 → DDR2 main clock, and ∈DDR2/mDDR PHY controller What is PHY controller? Interface with CPU & other peripherals...
    on Mar 21, 2012
  • Forum Post: RE: Help check am1808 ddr2 configuration

    robert chen97444 robert chen97444
    We found that the "scrolling stream" problem was caused by unconnected DDR_DQGATE0 and DDR_DQGATE1 pins on our board. To workaround this, we configure EXT_STRBEN=0 (Internal strobe gating mode) in DRPYC1R register. The scrolling problem disappears . (but the ddr2 still doesn't work...
    on Dec 24, 2012
  • Forum Post: RE: Help check am1808 ddr2 configuration

    robert chen97444 robert chen97444
    Thank you for the explanation. One more question: Suppose the sum of the four parameters exceed the pre-amble window width, is there a way to compensate this by configuring some registers? Since what's done is done on our board, we manage to let the board work with Internal Gating Mode at this...
    on Jan 3, 2013
  • Forum Post: DDR2: Arbitrary 2X_CLK for fixed VCLK?

    Paul Singh Paul Singh
    Hi, We would like to ask a question on DDR2 controller of L138. According to “7.3.2 DDR2/mDDR Memory Controller Clocking” of TRM SPRUH77, VCLK is sourced from PLL0_SYSCLK2/2 2X_CLK is sourced from PLL1_SYSCLK1 And it appears that the two clocks are completely INDEPENDENT. For...
    on Mar 27, 2013
  • Forum Post: Help check am1808 ddr2 configuration

    robert chen97444 robert chen97444
    Hi, we use am1808 + ddr2 on our custom board. The ddr2 just can't work. We have tried many configurations hard and still failed. This becomes a bottleneck of bringing up the board. DDR2 (1Gbits, 16-bit) : K4T1G164QF-BCE6 DDR2 memory controller configurations : see attached excel file...
    on Dec 20, 2012
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