OMAP™ Processors

Browse by Tags

OMAP™ Processors

Welcome to the OMAP™ Processors Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

Sign In to Post
Tags
You have subscribed to this tag. To view or manage your tag subscriptions, click here.   Close
You have unsubscribed from this tag. To view or manage your tag subscriptions, click here.   Close
You are currently viewing:
DDR
Related Posts

  • Forum Post: Re: Writing and Reading SDRAM with OMAP-L138

    BrandonAzbell
    Joe Tijerina I'm working with a omap L138 eXperimenter kit and need to write data samples to external SDRAM from the ARM and then have the uPP dma transfer those samples to an external peripheral. Can the ARM write to external memory? If so, can you point me to a guide or example on how to do...
    on Oct 24, 2009

  • Forum Post: How to patch kernel 2.6.29 to support 512MB DDR SDRAM on OMAP3?

    Ruchi
    Hi all, I am working with Linux kernel 2.6.29 and OMAP3 for development. Recenlty I was asked to patch the kernel to support 512MB DDR SDRAM. I came across the following link, http://wiki.omap.com/index.php/HOWTO_Support_512MB_SDRAM Unfortunately, the patch provided in this link is for an older kernel...
    on Nov 5, 2009

  • Forum Post: OMAP-L138 NOR Flash Writer on Custom Hardware

    Che
    Dear forum! I have a custom hardware platform with an OMAP-L138, a 32MB DDR2, and a 32MB NOR flash. Im using the setup shown below: Windows 7, 64bit XDS100v2 style emulator (from OPELLA) CCSv4 (4.1.1.00014) 20MHz input quarz on my board Ive been able to connect to the device ...
    on Apr 23, 2010

  • Forum Post: OMAP-L138 - using EMIFB DDR by DSP and ARM simultaneously

    Wojciech
    Hi Sorry for my english I got Zoom OMAP-L138 Experimenter Kit and OMAP-L138 SOM-M1 64M DDR. 1. ARM works with Linux kernel and it uses 32M space of EMIFB DDR (0xC000 0000 - 0xC1FF FFFF). Can ARM and DSP use EMIFB DDR simultaneously (on example DSP will use the remaining 32M space of EMIFB...
    on Aug 19, 2010

  • Forum Post: [OMAPL138] DDR Physical layout

    Dunham Williams
    DDR routing question My question has to do with determining the 'Target' length of my routes for the net class that is referred to in Table 6-35 on page 123 of OMAP-L138 Low-Power Applications Processor (SPRS586A–JUNE 2009–REVISED AUGUST 2009). I need to know how to correctly interpret...
    on May 14, 2010

  • Forum Post: L138 DDR Timing Analysis tool

    tehoaislimau
    Hi Is there a timing analysis tool already available that allows uses to test how much timing margin the board design has on the DDR bus? This is to specifically test timing marginallities caused by implementation, layout and or different memory vendors.
    on Sep 17, 2010

  • Forum Post: DDR2 differential clock termination

    fdm
    Is it true what there is no need of parallel (100 Ohm diff) termination of the differential clock signal (DDR_CLKP/DDR_CLKN) and moreover - according to the OMAP-L138 datasheet - " ... serial terminations are the only type permitted " also true for this case?
    on Apr 13, 2011

  • Forum Post: Re: omapl138 <> micron 256Mb DDR2 problem

    Cor
    Hello Jeff, 1) I use series resistors off 22ohms on all lines 2) The revision is MT47H16M16BG-3:B 3) Yes I tried this at tCK is 8ns->125MHz which is the lowest clock for this ddr2 -3 4) Yes I started with the spreadsheet. and then afterwards I used the SPRUGJ4B user guide to understand...
    on Apr 21, 2011

  • Forum Post: Re: omapl138 <> micron 256Mb DDR2 problem

    Cor
    Hi Jeff, Due to an isolation problem in one of the layers the ddr_dqgate0 was shorted to ground. I got a strange behavior of the ddr2 by this fault. regards, Cor
    on Apr 28, 2011

  • Forum Post: OMAPL138 DDR2 Interface Terminators

    ben zhan
    hi, I use two K4T1G084QF-BCF7 8bits DDR2 chips to connect on Omapl138 DDR2 Interface to be a 16bits 256Mbytes DDR2. One is the upper byte, another is lower byte. Should i connect the Terminator? Last version of my board,use a single 16bits DDR2 chip , I did't connect the Terminator. Do you...
    on Jun 22, 2011

  • Forum Post: Re: I have a new PCB board use the AM1808B zwt ,when I use the sfh_OMAP-L138.exe to reflash the chip ,

    francis kumar
    Hi, We are also facing with same Boot issue. When ever trying to load using SPI with sfh_OMAP-L138 -erase command, its is giving message "waiting for SFT on the OMAP-L138" it stuck there always. Anyone can suggest on my problem. Francis Kumar
    on Sep 21, 2011

  • Forum Post: Re: ddr2 on OMAPL138

    yugy
    I have some clues here .In the cmd file,if the sections setting as below,The read write are ok.But if when I added dsp/bios,the program can't run.It stops in the initialization.I don't know why.I think ddr2 may need special SECTIONS setting. MEMORY { IRAM: o = 0x80000000 l = 0x00020000 /*...
    on Sep 23, 2011

  • Forum Post: DDR2 PLL configuration for OMAP L138 at 375/456 MHz clock

    Andreas44690
    Hello, Can you please confirm the following: 1) spruh77, figure 15-2: VCLK has the upper limit of 114 MHz (PLL0_SYSCLK2 at 228MHz) / 93.75MHz at 1.3V / 1.2V, respectively but VCLK has no lower limit. 2) It is mandatory to have VCLK (228MHz / 2 maximum) lower than 0.5*2X_CLK (125 MHz minimum...
    on Sep 27, 2011

  • Forum Post: OMAP L-137 putting SDRAM in self refresh mode in DSP bootloader

    Armand Ciejak
    I'm trying to set the SDRAM in self refresh mode from the DSP bootloader without success. I'm working on a custom board derived from the DA8XX EVAL board. I have implemented what is documented in the SPRUFL7A in chapter 2.6.7, but the SDRAM goes into self refresh only if I execute the code...
    on Oct 3, 2011

  • Forum Post: AM1808 wake up from low power mode using interrupt.

    Nirav Patel72643
    Hi all, I am using AM1808 based handheld device. I am able to go in the low power mode using echo mem > /sys/power/state command. But I want to come out from this with GPIO based interrupt line. So if anybody knows how to come out from low power mode with some GPIO interrupt line. ...
    on Oct 11, 2011

  • Forum Post: use the iar and jlink connect to the AM1808

    token
    hello, now , I use the iar and jlink to develop my project, but i only debug program with iram debug option, I can't use the ddr debug option. in ccs, we can use the gel file to init ddr,nor,nand. but how to do it in IAR IDE system? Thanks. Token
    on Oct 18, 2011

  • Forum Post: DDR2 initialization on OMAP-L138

    Boris Ruvinsky
    Dear E2E: Thank you for your help. I modified the GEL file which came with Evaluation board. I modified the GEL file because I use DDR2 - not mDDR which is on Evaluation board. The SDRAM Controller on OMAP-L138 was setup correctly with modified GEL file: 1. All clock including DDR2 clocks...
    on Oct 26, 2011

  • Forum Post: Re: DDR2 initialization on OMAP-L138

    Boris Ruvinsky
    Hi Jeff. Thank you for your respond. DDR2 SDRAM is OK now. I used GEL file for SDRAM initialization and found some bugs in code. Thank you, Boris
    on Nov 30, 2011

  • Forum Post: Error on malloc() function for OMAP-L137 DSP

    Eugene C
    Hi, I am using OMAP_L137 DSP non-BIOS. There is a 16-bit DDR RAM connecting to the EMIF_B port. I need create a big float array (4096 entries) using the malloc() function below. However, it reports memory allocation error. If I reduce the size of the array from 4096 to 256, then everything is fine...
    on Nov 15, 2011

  • Forum Post: The CIO command cmd:(40) in the CIO buffer at address (0xc101bfb0) was not recognized. Please check the device and program memory maps

    ben zhan
    hi, I designed a board which apply with LogicPD OMAPL138_EVM, On my board ,this is a 512MB nandflash, but when I test the nandflash use nand_test.out,some errors occurs below: ------------------------------------------------------------ Starting DA8xx_NANDWriter. DA850/OMAP-L138 part detected...
    on Nov 29, 2011

  • Forum Post: OMAPL138 DDR and Nandflash error

    ben zhan
    hello, I got a problem ,ti is very strange. when i test ddr2 independent in ccs3.3 , test passed. and I test nand flash in the internal RAM of DSP in ccs3.3 ,test passed too. when I test DDR2 and Nandflash together, test failed. The data writed in the flash is not match with the data readed out...
    on Nov 29, 2011

  • Forum Post: DDR2: Exact routing specification for OMAP L138?

    Anonymous Anonymous
    Hi, I would like to ask a question on OMAPL138 DDR2 routing. OMAP L138 DM643x (1) Implementing DDR2 PCB Layout on the TMS320DM643x DMSoC , SPRAAL6 ✓ (2) Understanding TI's PCB Routing Rule-Based DDR...
    on Nov 8, 2011

  • Forum Post: L138 DDR2 Layout -- yet more questions

    Joe Curren57439
    Greetings-- To continue on Zheng's topic of last month: I'm using one x16 DDR2 part with L138-ZWT. 1. The datasheet specifies length mismatches (Tables 5-36,37,38), but my layout tool is "helping" by equalizing in time units. I've extracted the inner layer tpd rate at 6.8 ps...
    on Jan 23, 2012

  • Forum Post: OMAP-l138 ADDR_CTRL & D routing

    Mohammad Ali Koteich
    Hi, My stack up is (8layer): Top PWR GND Highspeed 1 Highspeed 2 GND PWR Bottom My question is if it's possible to use both highspeed layers to route the ADDR_CTRL net class, or does the entire netclass have to be routed on the same layer? Same question applies...
    on Feb 28, 2012

  • Forum Post: AM1808: memory allocation with BSL

    Alexey Golovizin
    Hi. I have an AM1808 experimenter kit. I want to get access to DDR memory using the BSL packages provided with my board, without any OS. I use AM1808.gel script for initializing memory. What is the standard way to use DDR memory in such case?
    on Mar 19, 2012
12

All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site. TI, its suppliers and providers of content reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

TI Worldwide | Contact Us | my.TI Login | Site Map | Corporate Citizenship | mobile m.ti.com (Mobile Version)

TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs and
embedded processors, along with software, tools and the industry’s largest sales/support staff.

© Copyright 1995-2013 Texas Instruments Incorporated. All rights reserved.
Trademarks | Privacy Policy | Terms of Use