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  • Forum Post: [HW] DDR2 selection OMAP-L138/TMS320C6748

    MMax
    Hi all, I'm new to this TI community, I hope to find here some TI experts and "collegue" to discuss commun problems :). I'm looking for NON mobile DDR2 (extended temp range -40 +85C) that may match the DDR2 controller (max 150Mhz clk). At Micron Tech., for example , there aren't...
    on Sep 15, 2009

  • Forum Post: Re: Writing and Reading SDRAM with OMAP-L138

    BrandonAzbell
    Joe Tijerina I'm working with a omap L138 eXperimenter kit and need to write data samples to external SDRAM from the ARM and then have the uPP dma transfer those samples to an external peripheral. Can the ARM write to external memory? If so, can you point me to a guide or example on how to do...
    on Oct 24, 2009

  • Forum Post: OMAPL138 Memory Map Configuration

    Joe Tijerina
    I am using one of the examples (message) from the dsplink package for the OMAPL138 as my starting point. I have identified some files that are used for memory map configurations. Under the message sample dir, there were a few others 1) message/message.tci 2) message/DspBios/5.XX/OMAPL138GEM...
    on Mar 1, 2010

  • Forum Post: External memory best use on OMAPL138

    Jonathan Journo
    Hello, We are developping an application on the OMAPL138 that make the use of the ARM and DSP core separately because they are doing different tasks. We planed to use Linux as GPP OS and DSP/BIOS for DSP. Codec Engine was not a good solution for us so instead we decided to use DSPLINK directly to...
    on Aug 5, 2010

  • Forum Post: Re: SDRAM question in OMAP-L138

    Jonathan Journo
    hi, Yes you should be able to find memories that allow you to hook up upto 512 MBytes for DDR2 or 256 MBytes for mDDR. The only limitation is that you are only allowed to a 1x16 or 2x8 memory configuration (as specified in the datasheet, see snapshot below), a 4x4 memory configuration is not...
    on Sep 13, 2010

  • Forum Post: L138 DDR2 boot up time

    Wes Hubbell
    Hello, - very preliminary stages of L138 design and doing some memory planning... #1 DDR2RAM For our application of the L138 (OMAP-L138-ZWTA3), during boot up, we need to put all memory locations in the attached DDR2 RAM into a known state (or check each location) - does anyone have experience in...
    on Nov 23, 2010

  • Forum Post: [OMAPL138] DDR Physical layout

    Dunham Williams
    DDR routing question My question has to do with determining the 'Target' length of my routes for the net class that is referred to in Table 6-35 on page 123 of OMAP-L138 Low-Power Applications Processor (SPRS586A–JUNE 2009–REVISED AUGUST 2009). I need to know how to correctly interpret...
    on May 14, 2010

  • Forum Post: Question with OMAP L138 DQGATE routing

    Anonymous Anonymous
    Hi, I would like to ask some questions with OMAP L138 DDR2 controller DQGATE routing. Length I found that there is some ambiguity in the expression for CKB0B1. Does “CK net” refer to a net class or nets? To interpret it as CK net class, we have support in Table 5-33; ...
    on Dec 27, 2011

  • Forum Post: OMAP-l138 ADDR_CTRL & D routing

    Mohammad Ali Koteich
    Hi, My stack up is (8layer): Top PWR GND Highspeed 1 Highspeed 2 GND PWR Bottom My question is if it's possible to use both highspeed layers to route the ADDR_CTRL net class, or does the entire netclass have to be routed on the same layer? Same question applies...
    on Feb 28, 2012

  • Forum Post: DDR2 corners in traces

    Mohammad Ali Koteich
    Hi there helpful folks! Thanks to your help I've come a bit further with my design (8 layer PCB based on OMAP-L138). My question this time arise out of a slight confusion from reading your documents. In the USB2 layout guidelines (SPAAR7) it is mentioned that one should not use 90 degree turns...
    on Mar 2, 2012

  • Forum Post: Connecting bypass capacitors. Directly or through plane?

    Mohammad Ali Koteich
    Figures: http://www.sigcon.com/images/news/9_07a.gif In this article: http://www.sigcon.com/Pubs/news/9_07.htm Doctor Johnson discusses why it's better to connect power pins in accordance to figure 1a, rather than 1b. (to avoid inductance caused by the direct connection). However, in the...
    on Mar 14, 2012

  • Forum Post: AM1808 DDR2 Memory Controller's maximum frequency ?

    robert chen97444
    Hi, I use AM1808 EVM. Does AM1808's memory controller have a maximum frequency or frequency limitation ? Is it 150 MHz ? (There is a related sentence mentioned in SPRUH82A.pdf , page 127. But it may just an example...) We use 128MB DDR2-800 in our design. Will it be limited to that...
    on Apr 3, 2012

  • Forum Post: Re: Hawkboard Issues - TI Annoucement

    Phillip Warren104258
    what's the postmortem analysis of the hawkboard tell about the root cause of the failure? did the designers follow the datasheet correctly? did the TMDXLCDK138 designers follow the datasheet recommendations and have issues, hence the delays? we're about to start a design and a lack of a TI designed...
    on Apr 20, 2012

  • Forum Post: RE: Hawkboard Issues - TI Annoucement

    Phillip Warren104258
    Thanks. Do you have an ETA for when the reference design files will be available? Are you planning to publish data on the radiated emissions measurements of the reference design?
    on Apr 25, 2012

  • Forum Post: "Skew Length Mismatch" in OMAP-L138 Datasheet

    Mohammad Ali Koteich
    Hi, In section 5.11.3.11 on page 136, Table 5-36, row 2, the following line can be found: "CK A to B/A to C Skew Length Mismatch-------------------- MAX: 25 Mils" 1. What in the world is "skew length mismatch"? I'm sorry, I'm fairly new to PCB design, and I...
    on Nov 15, 2011

  • Forum Post: DRPYC1R[13] bit have been reserved different from silicon errata description.

    RY9983
    Hello, I have been trying to improve ESD Immunity on OMAPL138. The usage note on silicon errata describes the following: (sprz301g: P7) Disable the DLL REFCLK signal in the DDR EMIF PHY. This prevents the DLL used by the DDR PHY from dynamically tracking glitches on the input clock. This can be done...
    on Apr 12, 2012

  • Forum Post: RE: Help check am1808 ddr2 configuration

    Sunil Kamath
    Robert, Both internal and external modes are reliable if used as recommended.Strobe gating is employed to avoid glitches on the strobe lines to be detected as valid strobe edges. The Internal Strobe Gating Mode (EXT_STRBEN=0) can ONLY be used for low frequency operation - i.e. when the board and...
    on Jan 2, 2013

  • Forum Post: SDTIMR1

    Mandeep Bansal
    Hello E2E, I'm working to configure DDR2/mDDR memory controller on AM1808 with MT47H64M8. Basically, following section 14.2.13.1 of AM 1808 Technical Reference. One of the steps is to configure SDTIMR1 and SDTIMR2 register to the desired values to meet the memory data sheet specification. Does...
    on Feb 1, 2013

  • Forum Post: DDR2 clock on OMAP-L138

    Yan8622
    Hi, Someone told me that the DDR2 clock can't go higher than 150Mhz because of a physical limitation of the omap chip, is that true? Thanks
    on Feb 7, 2013

  • Forum Post: L137 SDRAM vs L138 DDR2 comparison

    Kaan Dogan1
    Hi guys. I had been working with c6747 for quite some time, and I am also familiar with L137. I am considering C6748 and L138 for my future work( because of upp, 2 sd card support, 475 Mhz possibility). I need performance data access of "133 Mhz 32 bit SDRAM access in C6747" (and 16 bit version...
    on Feb 6, 2013

  • Forum Post: about deciding the round trip board delay on AM1806 DDR I/F

    RY9983
    Hello. I am gonna use DDR2 SDRAM as memory of AM1806. I would like to ask you about deciding the parameter of DRPYC1R->RL field. The DRPYC1R->RL portion is related elapsed time of the round trip. Even if round trip time on our target board is 10nsec and DDR_CLK is 150MHz, I think it is calculated...
    on Mar 3, 2013

  • Forum Post: DDR2: Arbitrary 2X_CLK for fixed VCLK?

    Paul Singh
    Hi, We would like to ask a question on DDR2 controller of L138. According to “7.3.2 DDR2/mDDR Memory Controller Clocking” of TRM SPRUH77, VCLK is sourced from PLL0_SYSCLK2/2 2X_CLK is sourced from PLL1_SYSCLK1 And it appears that the two clocks are completely INDEPENDENT. For...
    on Mar 27, 2013

  • Forum Post: Can L138’s DDR2 run at 25MHz?

    Karl Garcia
    Hi, What is the lowest allowable frequency of a DDR2 which is connected to an L138 ? For example, on page 30 oaf Micron MT47H64M16( product page )’s datasheet , the MAX clock cycle is listed as 8.0ns, which suggest lowest frequency is 125MHz. However, in page 81 of the same document, it seems...
    on Apr 15, 2013

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