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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » OMAP™ Processors » OMAP-L13x, AM1x and C674x Processors Forum » All Tags » omap3530
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Welcome to the OMAP™ Processors Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

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omap3530
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Related Posts
  • Forum Post: Re: Issue With Running Demo from Codec Engine and cmemk.ko loading

    ddompe ddompe
    Vineet, I wasn't aware you were using an initrd fs image (You see, we user our own SDK for OMAP35x that handles the filesystem allocation for us, and initrd is not used often for the memory dog it is). In this case I think you are better off using some NFS boot procedure or SD-card boot procedure...
    on Dec 12, 2008
  • Forum Post: video_encode_io1_omap3530.x470MV not working

    Vineet Vineet
    Hi, I am booting omap board from nfs server and my decode and display is working fine but I am unable to encode yuv file to .264 file and the following errors are coming:- [root@OMAP3EVM dvsdk]# ./video_encode_io1_omap3530.x470MV -c h264enc -r 352x288 -i test.yuv -o out.264 Starting application...
    on Jan 6, 2009
  • Forum Post: NFS in write mode issue

    Vineet Vineet
    I have setup NFS Server and booting FS but from board I am unable to save any file. However I created each and every directory with login as root/root permission. When I am pressing back key then previous commands are not shown on the OMAP board. It seems fopen() and fwrite is also not working and while...
    on Jan 10, 2009
  • Forum Post: Re: Segment conflicting in bios

    Brad Griffis Brad Griffis
    Sureshkumar, The L2 memory has two sections: Section 1: 32 KB of dedicated L2 SRAM Section 2: 64 KB configurable as cache or SRAM The default configuration comes with a section called IRAM which allocates all 96KB of L2 memory as SRAM. When you turn on the L2 cache you need to reduce the...
    on Jan 22, 2009
  • Forum Post: Re: TRACE32 JTAG debugger not showing tasks

    ddompe ddompe
    Hi, Are you using run-mode (with t32server) or stop-mode debugging? In stop mode it won't display anything while the processor is running. In run mode you need to use go.monitor to get the communication going. Diego
    on Jan 27, 2009
  • Forum Post: Re: Installation of xdais_6_22_01

    BrandonAzbell BrandonAzbell
    If you have access to the DVSDK for OMAP3, you will find examples. This should be located at http://www.ti.com/omapsoftwareupdates.
    on Feb 9, 2009
  • Forum Post: Re: XDAIS in CCS

    BrandonAzbell BrandonAzbell
    You should find this with the DVSDK for OMAP3 found at http://www.ti.com/omapsoftwareupdates.
    on Feb 9, 2009
  • Forum Post: Re: DVSDK and kernel versions

    ddompe ddompe
    Hi, Well, I would say if you have board support vendors they should probably care for supporting the software tools if they are moving to a newer kernel :S I understand that there are official plans in the future for OMAP SDKs to support git kernels (and therefore the DVSDK), but don't hold your...
    on Feb 19, 2009
  • Forum Post: Re: Need help with hardware-programming

    SabineKäß SabineKäß
    some weeks later: again, I am trying to solve my OMAP problem... [:P] By the way, I tried to analyse the delivered Linux drivers to get the needed information. But it is very difficult for me, since I am not trained in Linux programming. Project background: We want to run a virtualisation software...
    on Mar 19, 2009
  • Forum Post: Need help with hardware-programming

    SabineKäß SabineKäß
    Hello, I start working with the OMAP35x Evaluation Module and try to drive the lcd to display images. This has to be done as a native program directly on the hardware. The documentation of the OMAP35x is very voluminous and it is not very obviously recognisable to me which components and registers...
    on Nov 27, 2008
  • Forum Post: Re: GUI Developement

    Bernie Thompson TI Bernie Thompson TI
    For GUI development you may want to consider using something like the Angstrom distribution as seen on Beagle here , I believe it has GTK out of the box but even if it does not it is easy to bring it in.
    on Apr 7, 2009
  • Forum Post: Re: IO mapped IO, NAND and GPMC

    BrandonAzbell BrandonAzbell
    The need for specifying the base address is the indicate where the particular Chip Select region exists in the device memory map.
    on Apr 21, 2009
  • Forum Post: Re: McBSP to McBSP Configuration Problem

    BrandonAzbell BrandonAzbell
    Is this issue still open or do you have a resolution? Thank you.
    on Apr 21, 2009
  • Forum Post: Re: IO mapped IO, NAND and GPMC

    Nishanth Menon Nishanth Menon
    Shobhraj Singh I understand NAND address space is IO mapped IO. A NAND device is typically attached to a GPMC CS. Each of the GPMC CS' have a dedicated addressing space limited to 128/256MB. A GPMC register CONFIG7 takes the CS base address and length as inputs. I can understand filling up...
    on Apr 21, 2009
  • Forum Post: IO mapped IO, NAND and GPMC

    Shobhraj Singh Shobhraj Singh
    Sir, I understand NAND address space is IO mapped IO. A NAND device is typically attached to a GPMC CS. Each of the GPMC CS' have a dedicated addressing space limited to 128/256MB. A GPMC register CONFIG7 takes the CS base address and length as inputs. I can understand filling up these fields...
    on Mar 26, 2009
  • Forum Post: Re: IO mapped IO, NAND and GPMC

    Nishanth Menon Nishanth Menon
    BrandonAzbell The need for specifying the base address is the indicate where the particular Chip Select region exists in the device memory map. not if the device is a I/O Device
    on Apr 21, 2009
  • Forum Post: McBSP to McBSP Configuration Problem

    Stephane Grenier Stephane Grenier
    Hi All, I am trying to use McBSP1 has an inter-processor data link between two OMAP3530. I can write and read data on the buffers in digital loopback no problems; also I can see the data coming out of the interface on a digital scope. What I can not get is my receiver side to see the data. My basic...
    on Mar 26, 2009
  • Forum Post: Re: IO mapped IO, NAND and GPMC

    BrandonAzbell BrandonAzbell
    I disagree. I understand the point you are trying to make from a "need" perspective, but fundamentally the external NAND device will be connected to one of the gpmc_ncs[7:0] signals of the OMAP35xx device. This chip select needs to be configured AND enabled, in order for any accesses to occur...
    on Apr 21, 2009
  • Forum Post: Re: Rebuilding PSP 2.0 from source with bitbake

    BrandonAzbell BrandonAzbell
    I don't believe the OMAP35x Linux PSP Release 02.00.00.01 obtained from https://www-a.ti.com/downloads/sds_support/targetcontent/psp/omap35x/index.html is an Angstrom distro, nor uses bitbake to build. There is an OE/Angstrom recipe for the BeagleBoard. The instructions to build the Linux PSP are...
    on Apr 23, 2009
  • Forum Post: Rebuilding PSP 2.0 from source with bitbake

    John F. John F.
    Hello, I'd like to reproduce the kernel and root filesystem binaries from the PSP 2 release. Since this looks like an angstrom distro, I set up OpenEmbedded and bitbake, specified argstrom, the 35xevm, and the CodeSourcery toolchain with these lines in local.conf: DISTRO = "angstrom-2008...
    on Apr 22, 2009
  • Forum Post: Re: Linux LPM driver failing in Codec Engine 2.23.01 sanity_test/app.out

    Dirk Helgemo Dirk Helgemo
    Thanks, Ramsey. Yes, the device is OMAP3530, not sure what silicon revision. (I'll work on this in parallel with our discussion.) I'm not sure I can match up the LPM_off() code (in modules/omap3530/lpm_omap.c) exactly with your 7-step sequence, so instead here are the major comments (/* ...
    on May 4, 2009
  • Forum Post: Re: Linux LPM driver failing in Codec Engine 2.23.01 sanity_test/app.out

    Dirk Helgemo Dirk Helgemo
    CONTROL.CONTROL_IDCODE reads back a value of 0x2B7AE02F, so the silicon revision is ES2.1.
    on May 4, 2009
  • Forum Post: Re: Linux LPM driver failing in Codec Engine 2.23.01 sanity_test/app.out

    Dirk Helgemo Dirk Helgemo
    Commenting out your sections 1 and 2 (which correspond to my sections 1 to 7) still fails. (Looks nearly identical once I added code to print the IVA2 power control/status registers after failure.) Here is the output from running lpmOFF.xv5T: ==== LPM OFF Test ==== lpm.ko: --> LPM_off app: LPM_open...
    on May 4, 2009
  • Forum Post: Re: Linux LPM driver failing in Codec Engine 2.23.01 sanity_test/app.out

    Dirk Helgemo Dirk Helgemo
    I was also able to borrow a neighbor's ES3.1 on a Zoom dev kit, and got exactly the same result.
    on May 4, 2009
  • Forum Post: Re: Linux LPM driver failing in Codec Engine 2.23.01 sanity_test/app.out

    Dirk Helgemo Dirk Helgemo
    Thanks again! Unfortunately, the behavior is the same (added register print to your code, then ran lpmOFF.xv5T): ==== LPM OFF Test ==== lpm.ko: --> LPM_off app: LPM_open app: LPM_set(LPM_CTRL_REFCOUNTOVR) app: LPM_off lpm.ko: Error: IVA2 power domain not OFF (1) lpm.ko: PM_PWSTCTRL_IVA2 = 0x00FF0F04...
    on May 5, 2009
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