question about omap3530 I2C module.

Hi All:

         I am debugging the omap 3530 I2C module.

         Questions as below :

         1.when in Master Transmite mode.isr (interrupt),how to turn off the interrupt from the same source?

          ie:registers I2C_STAT[4] I2C_STAT[14] bits?

         2.if the register I2C_CON[15] is set to "0",when the previous status is "0".reset?

            else if the register I2C_CON[15] is set to "1",when the previous status is "1", reset?

  • Lu, you can use I2C_IE to enable/disable interrupts. I2C_CON is used to reset the whole I2C module.  These status bits should be set to 0 after reset.

    Regards,

    James

  • In reply to JJD:

    Thanks Jams:
    my question is...plz take a look at the code below:(quote from i2c-omap.c)
    requested isr by standard API request_irq.if the interrupt comes:the code
    would be get called...
    omap_i2c_isr(int this_irq, void *dev_id)
    {
            ......
            ......
            
            if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
                u8 num_bytes = 1;
                if (dev->fifo_size) {
                    if (stat & OMAP_I2C_STAT_XRDY)
                        num_bytes = dev->fifo_size;
                    else
                        num_bytes = omap_i2c_read_reg(dev,
                                OMAP_I2C_BUFSTAT_REG);
                }
                while (num_bytes) {
                    num_bytes--;
                    w = 0;
                    if (dev->buf_len) {
                        w = *dev->buf++;
                        dev->buf_len--;
                        /* Data reg from  2430 is 8 bit wide */
                        if (!cpu_is_omap2430() &&
                                !cpu_is_omap34xx()) {
                            if (dev->buf_len) {
                                w |= *dev->buf++ << 8;
                                dev->buf_len--;
                            }
                        }
                    } else {
                        if (stat & OMAP_I2C_STAT_XRDY)
                            dev_err(dev->dev,
                                "XRDY IRQ while no "
                                "data to send\n");
                        if (stat & OMAP_I2C_STAT_XDR)
                            dev_err(dev->dev,
                                "XDR IRQ while no "
                                "data to send\n");
                        break;
                    }
                    omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
                }
                ----------------------------------------------------
                turn off the interrupt?by set the stat registers
                corrosponding bits:
                
                omap_i2c_ack_stat(dev,
                    stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
                    
                if the action above is reset the I2C status but not
                diasble the interrupt.
                at the meanwhile still the data in the FIFO needed
                to send out.Will the mpu acknowage the interrupt
                from hardware?
                ----------------------------------------------------
                continue;
            }
            if (stat & OMAP_I2C_STAT_ROVR) {
                dev_err(dev->dev, "Receive overrun\n");
                dev->cmd_err |= OMAP_I2C_STAT_ROVR;
            }
            if (stat & OMAP_I2C_STAT_XUDF) {
                dev_err(dev->dev, "Transmit underflow\n");
                dev->cmd_err |= OMAP_I2C_STAT_XUDF;
            }
        }
        ---------------------------------------------------------
        here is the place where we need to disable the interrupt?
        or the interupt would be nested?
        ---------------------------------------------------------
        return count ? IRQ_HANDLED : IRQ_NONE;
    }

  • In reply to lu edward:

    hi jams:

    I think the question is after writing the SA register,in omap_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop),what cause the interrupt?

    fifo below or XDRY bits is "1" set auto?

    thanks james