The OMAP3530's TRM indicates that bit 6 of the PRM_RSTST register is "EXTERNAL_WARM_RST", which it says is set when a "Global external warm reset occurred".
Although it doesn't state it directly, I believe this bit refers to the sys_nreswarm signal. Is this correct?
The description indicates that it's an external signal warm reset. Does this mean that something outside the OMAP must have pulled sys_nreswarm down initially? On the other hand, is there something inside the OMAP that will drive sys_nreswarm low and still cause the EXTERNAL_WARM_RST bit to be set?
For example, the watchdog is supposed to cause sys_nreswarm to be asserted, but it sets bit 4 instead of bit 6.
Deleted in favor of the next submission
After further reading of the TRM, and some experiments, each of the internal sources of reset that would drive sys_nreswarm low from the inside, i.e. asserting sys_nreswarm_out, have their own bits in the PRM_RSTST register. So it looks to me like EXTERNAL_WARM_RST is indeed only set when the system resets because a signal originating outside the OMAP pulls sys_nreswarm low.
I would appreciate hearing from an expert if my understanding is wrong, however.
My question is a bit off the topic. However its related to PRM_RSTST only.
I have implemented a code to read PRM_RSTST of OMAP3530. I want to know the reason of the reboot of the chip. However, each time it provides the value as 0x0 only (independent of the method of reset).
Can you please provide some information on how are you reading the value from this register?
Thanks and regards,
I'm not sure I remember what I did, but the register was probably read very early in the x-loader code, since that's what runs first after boot.
Currently, I am trying to read it from ioctl GETBOOTSTATUS of the driver code kernel/drivers/watchdog/omap_wdt.c. However could not succeed. I am always getting the value of PRM_RSTST as 0x0.
I will try to add some code at x-loader or u-boot level.
Any pointers in this regard would be helpful.
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