i have configured tvout and tested using background and color bar output(both pal and nstc).
but while using dss digital output for tvout , output at tv is not proper. i am suspecting the problem with frame buffer address 1(DISPC_GFX_BA1).
i am using 640x480 at dss config and 720x482 at digi config for nstc output.
venc configs are done as mentioned in datasheet.
the output at tv is distorted in this case.
how i have to set DISPC_GFX_BA1 register and the description of internal buffer usage in this(interlaced mode).
Are you doing this under an OS or directly through register access?
The TV out resolution needs to be either 720x480 for NTSC or 720x576 for PAL. If your frame buffer is of a different resolution then you must either use a video pipe and scale, or crop/clip the image to fit.
Both these require more than just changing the BA registers.
Have a look at the following wiki article for information on how the frame buffers, pipes and outputs can be configured.
(http://wiki.omap.com/index.php?title=Category:OMAP35x may also be useful to you)
If you are working under Linux, which build are you using? You should be able to enable the tvout through V4L2/fbdev/ioctls without the need for direct register accesses.
If you are not using an OS and accessing the registers directly then I can send you some simple sample code which access the registers directly for video, graphics, scaled, non-scaled, LCD, TV etc....
Please mark this post as answered via the Verify Answer button below if you think it answers your question. Thanks!
Please mark this post as answered via the Verify Answer button below if you think it answers your question. Thanks!
i am using it in bios (direct access).
my intention is to use a standard image(ex: 640x480 image is dumped as an continuous array at a same location in all cases) for both vga/lcd and tvout, and by changing DISPC_GFX_ATTRIBUTES: GFXCHANNELOUT i should able to switch between TV and VGA/LCD. is it possible?
i hope configuration for tvout register(VENC for pal and nstc) are same as in the omap3530 datasheet (please mention if any changes required).
i am totally confused with BA1 register.
as per my understanding BA1 is used only in case of TVOUT(GFXCHANNELOUT set to 1), its used for getting odd line data of interlaced mode.
doubt: is it must to dump the oddline data in a separate buffer? or i can load BA1 with BA0+size of one line data?
if it is "BA0+size of one line data" then how internally it will use it to access next odd line data (even line as well)?
is it possible to have TVOUT and VGA/LCD at same time(with same output)?
which are the registers in DISPC have effect over TVOUT.
expecting some sample code as u mentioned.
thanks and regards.
There are a number of ways you can do this. It is even possible to have both active at the same time (as you can see from the Wiki page I mentioned).
For the TV out, there are a few things you need to do. If the source image is 640x480 then you need to either scale it to fit 720x480 or window the image on the 720x480 output necessary for NTSC (For PAL the size is 720x576).
Regarding the BA registers, for the TV out you need to configure BA1 to point to the start of the image and BA0 to point to the start of the second line. Then, the line step registers need to be set to (640xpixel size) so that each field will skip alternate lines.
If you want to scale the image to fit, then you need to use a video pipe and not a graphics pipe.
One thing to note with most TVs... They will usually clip the outer 10% so that you will not see anything on the very top, bottom, left or right. Some TVs do more than 10%, some do less, but 10% is a good approximation.
To avoid this you may want to actually scale your image down for the TV out and center it on the output display.
e-mail me at firstname.lastname@example.org and I will send you some sample code to help you.
now its fine. but i faced small flicker in NSTC mode(with typical configuration as in data sheet), then used the settings for NSTC from some reference code and solved it.
also in above reply,
Regarding the BA registers, for the TV out you need to configure BA1 to point to the start of the image and BA0 to point to the start of the second line.
is it correct or is it like this?
Regarding the BA registers, for the TV out you need to configure BA0 to point to the start of the image and BA1 to point to the start of the second line.
It should be the first one :)
Here is a snippet from my code example...
WritePhysical(DISPC_VID1_BA1 + VidOffset, (unsigned int)Attributes.Buffer.BufferPtrs.PtrPBuffer + BufferOffset); WritePhysical(DISPC_VID1_BA0 + VidOffset, (unsigned int)Attributes.Buffer.BufferPtrs.PtrPBuffer + BufferOffset + ((Attributes.Buffer.Width * BPP / 8)));
Hi Devakumar ,
Please share the reference code to solve the flicker issue for OMAP NTSC TV OUT .
I am drawing(actually Android / Qt) some graphics on to the Graphics overlay and displaying on a TV, and running Linux 2.6.32 kernel. The mode argument for kernel commandline is "tv:ntsc". I have the use case of Graphics and Video overlay blending while video playback happens.
1. The problem is that the graphics, video always seem to be cropped from left, right , top and bottom while in TV mode. This does not happen when I configure it to use VGA display. I am relating this to what, you have said in earlier mail, that the TVs usually clip the outer 10%.
What would you suggest seeing the use-case and OS scenario?
2. Is it possible to display both on TV and VGA at the same time, considering that I have to blend video and graphics while playing videos?
What approach, would you suggest in this case?
I have tried somethings on my side before writing here to seek guidance. I have tried to modify the xres and yres in the omap_dss_ntsc_timings structure in venc.c to bring down the resolution to some value that fits within the TV screen. But not all combinations of xres and yres are OK, as I get "Out of Sync" error for most of the new values of xres and yres which I try.
Also did some modifications to VENC registers, but don't know how to arrive on the set of values which are correct to fit the Graphics on to TV. Can you point me to some document, which explains this in detail?
Thanking you in advance and wating for your inputs,
Sorry you are having trouble. Overscan is always an issue since not all TVs perform it and you cannot ever really be sure just how much a particular TV will do.
There are 2 options to correct for this TV induced overscan.
1) Reduce your source image size to about 640 x 425 then center it on the TV out.2) Scale your source image down to about 640 x 425 then center it on the TV out.
Option 1 is the simplest and most efficient in terms of memory bandwidth but obviously reduces your active frame buffer area.
Option 2 will end up doubling the memory bandwidth requirements since vertical scaling of an interlaced image requires 2x image reading. This option will, however, allow you to view your entire original frame buffer.
I will have to defer to folks who know more than me regarding the linux drivers and the current options for scaling through the Linux OS & drivers.
I have attached some register level configuration code which may help if you want to access the hardware directly. Be aware though that this code is very much development code and therefore should really only be used to help describe how the registers behave.
Thanks for the inputs.
I did try the following things today and also attaching the images of how my TV screen looks and hows the Graphics still getting cut from left and top side. Before doing this experiment I had changed the values of VENC registers to those sent by you in the previous code. After that I modified some of the register values, which I will mention below.
I wrote 720, 480/2 to the DISPC_SIZE_DIG. I allocated frame-buffer of size 684x456 and generated graphics of same size and wrote it to the framebuffer. I think, thats what the code you sent is trying to do(though it uses a 640x480 image).
Please let me know if this approach is correct. These are my VENC register values finally and the pictures which I am sending you correspond to these values.
Is there a document TI specific or general which you can point me to , which will help me understand the significance if these registers and terminology in more detail and what effect their values have on screen size? What is Hsync internal Vs Hsync external ?
.f_control = 0,
.vidout_ctrl = 0,
.sync_ctrl = 0x8040, //RBee
.llen = 0x359,
.flens = 0x20C,
.hfltr_ctrl = 0,
.cc_carr_wss_carr = 0x043F0000,
.c_phase = 0,
.gain_u = 0x102,
.gain_v = 0x16C,
.gain_y = 0x12F,
.black_level = 0x43,
.blank_level = 0x38,
.x_color = 0x7,
.m_control = 0x1,
.bstamp_wss_data = 0x38,
.s_carr = 0x21F07C1F,
.line21 = 0,
.ln_sel = 0x00000015,
.l21__wc_ctl = 0x00001400,
.htrigger_vtrigger = 0,
.savid__eavid = 0x069300F4,
.flen__fal = 0x0016020C,
.lal__phase_reset = 0x00060107,
.hs_int_start_stop_x = 0x008D034E, //RBee
.hs_ext_start_stop_x = 0x000F0359,
.vs_int_start_x = 0x01A00000,
.vs_int_stop_x__vs_int_start_y = 0x020301A0,
.vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
.vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
.vs_ext_stop_y = 0x00000006,
.avid_start_stop_x = 0x03480078,
.avid_start_stop_y = 0x02040024,
.fid_int_start_x__fid_int_start_y = 0x0001008A,
.fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
.fid_ext_start_y__fid_ext_offset_y = 0x01060006,
.tvdetgp_int_start_stop_x = 0x00140001,
.tvdetgp_int_start_stop_y = 0x00010001,
.gen_ctrl = 0x00F90000,
Thanks and regards
I suggest that you also look at the following wiki page which explains what the hardware capabilities are. You might find that this makes things a lot clearer.
Simply reducing the frame buffer image size will not move its position, only its size. You also need to move the output image to the right and down. This is done through the graphics pipe control registers.
Do not make any changes to the TV out VENC settings. These MUST be as I sent in the example code in order to generate a standard NTSC video signal.
The register you need to touch, in your case for the graphics pipe, is DISPC_GFX_POSITION (0x48050488)
If your new frame buffer is 684 then in order to center your image you need to set the x position to be (720-684) / 2 = 18
Vertically set the y position to be (480-456) / 2 = 12
Thanks Steve to clarify... I will check it.
My Customer has the similar TV out problems using VID2.Customer conditions are: - Source Image Size = 800x480 - Display Size = 720x482 (NTSC) - Destination Size = 684x458 (90% NTSC) ...Case-1 = 648x434 (80% NTSC) ...Case-2 - Not changed VENC settings, same as Technical Reference Manual(spruf98r) table 15-69 Video Encoder Register Programming Values. - PRCM regs settings (0x48004e00)PRCM.CM_FCLKEN_DSS =0x00000007 (0x48004d00)PRCM.CM_CLKEN_PLL =0x80371037 (0x48004d30)PRCM.CM_AUTOIDLE_PLL =0x00000009 (0x48004d40)PRCM.CM_CLKSEL1_PLL =0x094c0c00 (0x48004e40)PRCM.CM_CLKSEL_DSS =0x00001002~~~~~~~~~~~~~~o Case-1 Trouble~~~~~~~~~~~~~~ - SYNCLOSTDIGITAL occured. - Display becomes black.~~~~~~~~~~~~~~o Case-2 Trouble~~~~~~~~~~~~~~ When customer sets the X position to be (720-648) / 2 = 36 and y position to be (482-434) / 2 = 24: - SYNCLOSTDIGITAL occured. - Display becomes black. (*) Same as Case-1
When customer sets the X position to be > 13 and y position to be >10: - SYNCLOSTDIGITAL occured. - Display becomes black. (*) Same as Case-1
When customer sets the X position to be < 13 and y position to be < 10: - Down-sampling established - Not centered the dawn-sampling image because x/y positions is not correct.
In Case-1/2, are there any down-sampling lmitations like LCD out described in errata(sprz278f) 2.1.20? Thanks in advance for your cooperation.
we r able to get the DM3730 display on TV using its TVOUT signals... but TVOUT signal stops coming if the LCD driver is configured for a resolution greater than 800*600....so what might be the problem???
we want to use the TV out @ 1024*768 resolution since our LCD panel resolution is 1024*768..... since we want to display on both tvout n lcd simultaneously
thnx u in advance ......
hi Steve, here is my DSS register dump......for 1024*600 resolution..... but no signal on tv..tv is blank...
DSS Registers: DSS_REVISIONNUMBER=0x00000020 DSS_SYSCONFIG=0x00000001 DSS_SYSSTATUS=0x00000001 DSS_CONTROL=0x00000038 DSS_SDI_CONTROL=0x00000000 DSS_PLL_CONTROL=0x00000000 DSS_SDI_STATUS=0x00000081 DISPC Registers: DISPC_REVISION=0x00000030 DISPC_SYSCONFIG=0x00001009 DISPC_SYSSTATUS=0x00000001 DISPC_IRQSTATUS=0x000081AE DISPC_IRQENABLE=0x00005240 DISPC Registers (Control): DISPC_CONTROL=0x0801830B DISPC_CONFIG=0x00000208 DISPC_CAPABLE=0x000003FF DISPC_DEFAULT_COLOR0=0x00000000 DISPC_DEFAULT_COLOR1=0x00000000 DISPC_TRANS_COLOR0=0x00000000 DISPC_TRANS_COLOR1=0x00000000 DISPC_GLOBAL_ALPHA=0x00FF00FF DISPC Registers (LCD): DISPC_LINE_STATUS=0x0000013B DISPC_LINE_NUMBER=0x00000000 DISPC_TIMING_H=0x0780C801 DISPC_TIMING_V=0x00F01400 DISPC_POL_FREQ=0x00023000 DISPC_DIVISOR=0x00010001 DISPC_SIZE_DIG=0x012002CF DISPC_SIZE_LCD=0x025703FF DISPC Registers (GFX): DISPC_GFX_BA0=0x82802000 DISPC_GFX_BA1=0x82802000 DISPC_GFX_POSITION=0x00000000 DISPC_GFX_SIZE=0x025703FF DISPC_GFX_ATTRIBUTES=0x000000AD DISPC_GFX_FIFO_THRESHOLD=0x03FF01FF DISPC_GFX_FIFO_SIZE_STATUS=0x00000400 DISPC_GFX_ROW_INC=0x00000001 DISPC_GFX_PIXEL_INC=0x00000001 DISPC_GFX_WINDOW_SKIP=0x00000000 DISPC_GFX_TABLE_BA=0x89A62000 DISPC Registers (VID 1): BA0=0x00000000 BA1=0x00000000 POSITION=0x00000000 SIZE=0x00000000 ATTRIBUTES=0x00000000 FIFO_THRESHOLD=0x03FF03C0 FIFO_SIZE_STATUS=0x00000400 ROW_INC=0x00000001 PIXEL_INC=0x00000001 FIR=0x00000000 PICTURE_SIZE=0x00000000 ACCU0=0x00000000 ACCU1=0x00000000 DISPC_VIDn_FIR_COEF_Hi _HVi _Vi: 0: H = 0x00000000 HV = 0x00000000 V = 0x00000000 1: H = 0x00000000 HV = 0x00000000 V = 0x00000000 2: H = 0x00000000 HV = 0x00000000 V = 0x00000000 3: H = 0x00000000 HV = 0x00000000 V = 0x00000000 4: H = 0x00000000 HV = 0x00000000 V = 0x00000000 5: H = 0x00000000 HV = 0x00000000 V = 0x00000000 6: H = 0x00000000 HV = 0x00000000 V = 0x00000000 7: H = 0x00000000 HV = 0x00000000 V = 0x00000000 CONV_COEF0=0x00000000 CONV_COEF1=0x00000000 CONV_COEF2=0x00000000 CONV_COEF3=0x00000000 CONV_COEF4=0x00000000 DISPC Registers (VID 2): BA0=0x82802800 BA1=0x82802000 POSITION=0x002A002C SIZE=0x00C90287 ATTRIBUTES=0x006183ED FIFO_THRESHOLD=0x03FF01FF FIFO_SIZE_STATUS=0x00000400 ROW_INC=0x00000001 PIXEL_INC=0x00000001 FIR=0x0BE10652 PICTURE_SIZE=0x025703FF ACCU0=0x01F00000 ACCU1=0x00000000 DISPC_VIDn_FIR_COEF_Hi _HVi _Vi: 0: H = 0x1b761bea HV = 0x243624ea V = 0x00000101 1: H = 0x2b730dee HV = 0x28371fe7 V = 0x000004fe 2: H = 0x3a6b00f4 HV = 0x2c361be7 V = 0x000008fb 3: H = 0x475ff6fa HV = 0x303516ea V = 0x00000df8 4: H = 0xef5151ef HV = 0x12333300 V = 0x0000f612 5: H = 0xf65f47ea HV = 0x163530fa V = 0x0000f80d 6: H = 0x006b3ae7 HV = 0x1b362cf4 V = 0x0000fb08 7: H = 0x0d732be7 HV = 0x1f3728ee V = 0x0000fe04 CONV_COEF0=0x0199012A CONV_COEF1=0x012A0000 CONV_COEF2=0x079C0730 CONV_COEF3=0x0000012A CONV_COEF4=0x00000205
i thought it will be helpful if i post a register dump for 800*600 resolution..... with 800*600 resolution my tv out signal is coming... im able display on tv... below is the tested n working register dump for 800*600 resolution....... pls try to compare both....and suggest me a solution...
DSS Registers: DSS_REVISIONNUMBER=0x00000020 DSS_SYSCONFIG=0x00000001 DSS_SYSSTATUS=0x00000001 DSS_CONTROL=0x00000038 DSS_SDI_CONTROL=0x00000000 DSS_PLL_CONTROL=0x00000000 DSS_SDI_STATUS=0x00000081 DISPC Registers: DISPC_REVISION=0x00000030 DISPC_SYSCONFIG=0x00001009 DISPC_SYSSTATUS=0x00000001 DISPC_IRQSTATUS=0x0000A1AE DISPC_IRQENABLE=0x00005240 DISPC Registers (Control): DISPC_CONTROL=0x0801830B DISPC_CONFIG=0x00000208 DISPC_CAPABLE=0x000003FF DISPC_DEFAULT_COLOR0=0x00000000 DISPC_DEFAULT_COLOR1=0x00000000 DISPC_TRANS_COLOR0=0x00000000 DISPC_TRANS_COLOR1=0x00000000 DISPC_GLOBAL_ALPHA=0x00FF00FF DISPC Registers (LCD): DISPC_LINE_STATUS=0x0000014F DISPC_LINE_NUMBER=0x00000000 DISPC_TIMING_H=0x0970273F DISPC_TIMING_V=0x01700103 DISPC_POL_FREQ=0x00020000 DISPC_DIVISOR=0x00010002 DISPC_SIZE_DIG=0x012002CF DISPC_SIZE_LCD=0x0257031F DISPC Registers (GFX): DISPC_GFX_BA0=0x82802000 DISPC_GFX_BA1=0x82802000 DISPC_GFX_POSITION=0x00000000 DISPC_GFX_SIZE=0x0257031F DISPC_GFX_ATTRIBUTES=0x000000AD DISPC_GFX_FIFO_THRESHOLD=0x03FF01FF DISPC_GFX_FIFO_SIZE_STATUS=0x00000400 DISPC_GFX_ROW_INC=0x00000001 DISPC_GFX_PIXEL_INC=0x00000001 DISPC_GFX_WINDOW_SKIP=0x00000000 DISPC_GFX_TABLE_BA=0x89A86000 DISPC Registers (VID 1): BA0=0x00000000 BA1=0x00000000 POSITION=0x00000000 SIZE=0x00000000 ATTRIBUTES=0x00000000 FIFO_THRESHOLD=0x03FF03C0 FIFO_SIZE_STATUS=0x00000400 ROW_INC=0x00000001 PIXEL_INC=0x00000001 FIR=0x00000000 PICTURE_SIZE=0x00000000 ACCU0=0x00000000 ACCU1=0x00000000 DISPC_VIDn_FIR_COEF_Hi _HVi _Vi: 0: H = 0x00000000 HV = 0x00000000 V = 0x00000000 1: H = 0x00000000 HV = 0x00000000 V = 0x00000000 2: H = 0x00000000 HV = 0x00000000 V = 0x00000000 3: H = 0x00000000 HV = 0x00000000 V = 0x00000000 4: H = 0x00000000 HV = 0x00000000 V = 0x00000000 5: H = 0x00000000 HV = 0x00000000 V = 0x00000000 6: H = 0x00000000 HV = 0x00000000 V = 0x00000000 7: H = 0x00000000 HV = 0x00000000 V = 0x00000000 CONV_COEF0=0x00000000 CONV_COEF1=0x00000000 CONV_COEF2=0x00000000 CONV_COEF3=0x00000000 CONV_COEF4=0x00000000 DISPC Registers (VID 2): BA0=0x82802640 BA1=0x82802000 POSITION=0x000E002C SIZE=0x01020287 ATTRIBUTES=0x006183ED FIFO_THRESHOLD=0x03FF01FF FIFO_SIZE_STATUS=0x00000400 ROW_INC=0x00000001 PIXEL_INC=0x00000001 FIR=0x094404F0 PICTURE_SIZE=0x0257031F ACCU0=0x00A20000 ACCU1=0x00000000 DISPC_VIDn_FIR_COEF_Hi _HVi _Vi: 0: H = 0x028002fe HV = 0x264c26fe V = 0x0000f4f4 1: H = 0x147df405 HV = 0x2f481ff6 V = 0x0000f8f2 2: H = 0x2974ea0b HV = 0x354916ee V = 0x0000fcf0 3: H = 0x3e66e50f HV = 0x3b450fe8 V = 0x000001f0 4: H = 0xe45353e4 HV = 0x08404012 V = 0x0000f008 5: H = 0xe5663ee8 HV = 0x0f453b0f V = 0x0000f001 6: H = 0xea7429ee HV = 0x1649350b V = 0x0000f0fc 7: H = 0xf47d14f6 HV = 0x1f482f05 V = 0x0000f3f7 CONV_COEF0=0x0199012A CONV_COEF1=0x012A0000 CONV_COEF2=0x079C0730 CONV_COEF3=0x0000012A CONV_COEF4=0x00000205
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