Hi,
We have connected the processor parallel data lines to the input of the sn75lvds83b lvds chip. We have connected AT070TNA2 V.1 chimei Innolux 1024X600 resolution display which works at 67Mhz pixel clock Max. The issue we are facing is that DSS_HSYNC, DSS_VSYNC,DSS_PCLK are showing correct reading on the CRO ,but we are not getting correct voltage reading on the DSS_ACBIAS pin which is connected to the LVDS chip. Please suggest a solution to resolve this. Our connections seems to be OK from the processor side to LVDS chip. We are seeing some lines (hsync and vsync) on the lcd ,but not correct images.
changes done in kernel:
1. Changed the pixel clock in lcd panel driver to 56Mhz
2. enabled DSS_ACBIAS pin in mode0 as output
I have attached the LCD datasheet which does not show any HSYNC and VSYNC configurable values for 1024x600 resolution.
Can anybody tell us what are the hsync,vsync horizontal front porch ,horizontal back porch,vertican front porch and vertical back porch we need to set it.
4263.AT070TNA2_LCD.pdf
regards
Hi Ranjith Kumar,
I'm also using the same LCD part number.
I have a problem in the displayed image.
Dots are seen on the image.
Can you please share the LCD timings which you used.
Details of the board I'm using:
Processor: DM3730
Linux version: linux.2.6.32
Thank you,
chavala