• Resolved

ETM/ETB base address on OMAP3 (CortexA8)

What is the address of the embedded trace microcell/buffer configuration registers?  I'd like to use the CToolsLib (ETMLib) code to access the trace data from within my code.  Specifically to grab the trace after a exception event occurs.  All the examples have cortex A15 and A9 locations.


  • Figured it out, I didn't realize the ETB and ETM are accessed through the EMU/Coresight interface off the L4.  Hopefully the CToolsLib code will work with the CortexA8 like it does for the other Arm and DSP archs.