I have a new board to use the DM6467ZUT7. I tried to change the registers to achieve the 364.5/729MHz. Here are the registers' change.
729 change / 594
PLL1M = 0x0000001A/0x00000015PLLDIV4= 0x00008006/0x00008005PLLDIV5= 0x00008009/0x00008007PLLDIV6= 0x00008009/0x00008007 PLLDIV8= 0x00008009/0x00008007PLLDIV9= 0x00008006/0x00008005
PLLCMD= 0x00000001 to confirm the change
I test the changes by a script to count a fix number and time it. The result is the 594MHz is running about 29 to 30 seconds and the 729MHz is running in 31 to 32 seconds. They are the same board same situation and the value is changed in the command line with (memrw).
Is there any performance test in 6467?
Are the changes correct?
Are you changing the PLL numbers at Linux kernel level - I am assuming this is as you mention you changed this through a script. I would strongly recommend it to change clock settings at UBL level rather than at uboot or kernel level. Clocks should be stabilized before you run u-boot or kernel.
I have attached device.c file that is part of UBL source code and provided with Flash_utils.tar.gz in separate email gives you indication on PLL settings for 729MHz and 594MHz - same needs to be transferred to UBL that you are using.
Hope that helps.
PS: Please mark this post as verified if you think it answers your question
Sorry forgot attachment - this time with device.c attachment.
It seems like the only way to change the DM6467 clock to 365MHz is in the UBL.
The setting will be different to the data sheet. We don't need to change div5 and div6
PLL1_DIV4 to 0x00008006
PLL1_DIV8 to 0x00008009
PLL1_DIV9 to 0x00008006
PLL1M to 0x0000001a
In the u-boot, I don't touch any register except the PLL1M to 0x1a again. In Kernel, it is totallly no effect.
I verify by the dhrystone and it has about 25% increase of the speed.
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