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8-bit MMC/SD on Mistral OMAP3530 EVM
This question is specific to the Mistral OMAP3530 EVM, so I don't know if this is the right forum for this question but I'll try anyway.
I'm working with Rev. G of the EVM and the WinEC7 BSP available on the TI website (BSP_WINCE_ARM_A8_01_02_00), and I'm trying to enable the SD slot in 8-bit bus width mode. Product documentation indicates this is supported so I think I should be able to make it work, but I ran into a number of issues with the BSP's host controller implementation. Most of those were issues in platform\common\src\soc\COMMON_TI_V1\COMMON_TI\SDHC\BASE\SDHC.cpp which did not seem to be finished for supporting 8-bit mode, but I think I have most of these fixed. However, there is at least one issue remaining- half of the bus (DAT4-DAT7) does not seem to be functioning. These lines always read as zero.
After researching this I have realized that I still need to manipulate the host controller's CONTROL_PBIAS_LITE register to enable power to both halves of the bus. I think I understand how to do that but another question has come up. The GPIO signals that are connected to DAT4-DAT7 are enabled by the CONTROL_PBIAS_LITE settings, but ultimately get thier power from the VDDS_SIM (a.k.a. VDDS_MMC1a) pin. I don't know what register to set in order to be sure the appropriate voltage is applied from the PMIC to this signal, and in fact I don't know if this pin on the processor is connected to anything at all on the Mistral OMAP3530 EVM.
So my questions about the Mistral OMAP3530 EVM are:
Thanks in advance.
I seem to have gotten this to work simpy by enabling the appropriate PWRDNZ and VMODE bits for MMC1a in the CONTROL_PBIAS_LITE register of the host controller. This tells me that the voltage I want (3.3v ) is already present on VDDS_MMC1a. However, I'm still faced with two issues; one I've already mentioned and a new one.
Followup on my update:
The OMAP3530 TRM clearly states that the MMC bus testing procedure is supported by the MMC/SD/SDIO host controller present in the processor, in the 5th bullet point of paragraph 22.1.1, which states "Full compliance with MMC bus testing procedure as defined in the Multimedia Card System Specification, v4.2" I therefore have to believe this can be made to work, but I haven't been able to.
In the BSP's code that sets up the MMCHS_CMD register I modified the existing support for CMD19 and CMD14 to set the Data Present flag, set the Response Type field to indicate a length of 48 bits without using the DAT0 "BUSY" indication, and to identify it as a normal command in the Command Type field. For CMD19 I set the DDIR bit to indicate transfer from host to card (the existing code in SDHC.cpp actually already did this). DMA is enabled and works fine for other commands involving data transfer. It goes on to issue the command and start the BUS_TEST data transfer, and that seems to be going ok, but it eventually fails with a Data Timeout (DTO bit set in the MMCHS_STAT register).
What else do I need to do?
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