We are working on a custom platform based on Variscite SOM which is based on DM3730. Since single I2C bus is available from SOM, we are using CP2120 SPI2I2C adapter to connect some of our I2C devices. We are seeing extra delays in I2C transfers and debugging in to this issue.
We observed Ref clock for SPI controller is 48M_FCLK. We are programming clock divisor MCSPI_CHxCONF (5:2 CLKD) to get desired spim_clk. What we observed is Duty cycle of the resultant clock is not stable. It is keep varying and so we are not sure how much exact clock we are getting. We have connected Camera Sensor on this SPI2I2C adapter and it is taking more time for sensor I2C register configuration. We wanted to increase the SPI clock but not sure what is happening when we change divisor because of the unstable duty cycle.
Is anyone facing issues with unstable SPI clock?
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