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First PWM pulse is incorrect

Hi,

I'm using a OMAP 3530 processor - Timer8 to generate a PWM pulse of 50% duty cycle. The first pulse generated alone is of double the expected width and rest are generated properly.

I checked the register configurations and listed below:

Phy. addr : 0x4903 E000

  1. TCLR = 0x1843
  2. TLDR = 0xffb0bbcb
  3. TMAR = 0xffd85de6
  4. TTGR = 0xfffffff

Here, the TCLR[7].SCPWM bit is not set and Figure 16-12 depicts the pulse timing diagram for above settings. But when I probe, the first pulse is incorrect and doesn't match the Figure 16-12.

I don't know why the first pulse alone generated like that and tried to rectify the issue by changing the TCLR[7].SCPWM bit as 1. The issue got resolved and pulse generated was correct with 50% duty cycle.

Note:

dmtimer.c file was referenced and omap_dm_timer_set_load(), omap_dm_timer_set_match(), omap_dm_timer_set_pwm() interfaces were used.

Please reply me the cause for first pulse behavior and suggest whether the fix made is appropriate to resolve it.

Also the timing diagram Figure 16-12 and Figure 16-13 has the difference in the TCLR[7].SCPWM bit setting. I think the SCPWM bit and the timing diagram was interchanged i.e Figure 16-12 might have SCPWM bit as 1 and Figure 16-12 with 0.

  • Hi Pradeep,

    I'm trying to investigate this issue. I think your configuration is correct but I'm puzzled about TCLR[7].SCPWM bit setting. Could you confirm that if TCLR[7].SCPWM bit is 0 the timer start operating properly?

    BR

    Tsvetolin Shulev

  • Hi,

    With TCLR[7].SCPWM bit is 0, the issue occurs  i.e the first pulse alone becomes double the ON time (eg. 1 sec ON instead of 500ms ON). But pulse generated properly with 50% duty cycle from second pulse onwards...

    By setting TCLR[7].SCPWM bit as 1, the issue got fixed meaning the first pulse itself generated with 50 % duty cycle.

    I think it gives you some clue and Please let me know if you need more info.

    Regards - Pradeep khanna