I want to recevie VGA UYVY data from sensor .
sensor --> CCDC----> memory
parallel 8 bits.
how to config the registers of ISP and CCDC ?
this is my configration:
ISP_SYSCONFIG:
MIDLE_MODE =No-standby:
AUTO_IDLE = 0x1: Automatic clock gating strategy
-----------------------------------------------------------------------------------
ISP_CTRL:
ISPCTRL_CCDC_CLK_EN
ISPCTRL_CCDC_RAM_EN
ISPCTRL_RSZ_CLK_EN
SYNC_DETECT==0x2: VS falling edge
SHIFT = 0x3: Shift by 6 CAMEXT[13:6] - CAM [7:0]
|ISPCTRL_CCDC_FLUSH
|ISPCTRL_SBL_WR0_RAM_EN
|ISPCTRL_SBL_WR1_RAM_EN
|ISPCTRL_SBL_RD_RAM_EN
PAR_BRIDGE = 0x3: The bridge is enabled. The first byte is written toCAM.DATA[15:8], the second byte is written toCAM.DATA[7:0]
PAR_SER_CLK_SEL= 0x0: Selects the 12-bit parallel interface as the input tothe CCDC module.
------------------------------------------------------
IRQ0ENABLE :
IRQ0STATUS_HS_VS_IRQ |
IRQ0STATUS_RSZ_DONE_IRQ |
IRQ0STATUS_CCDC_VD0_IRQ |
IRQ0STATUS_CCDC_VD1_IRQ;
----------------------------------
CCDC_CFG:
VDLC == 0x1: Not latched on VS
-------------------------------------------------------
CCDC_SYN_MODE
17 WEN ==1 Data write enable.
16 VDHDEN = 0x1: Enable;
13:12 INPMOD = 0x1: YCbCr data on 16 bits. It is required to enable the 8to 16-bit bridge in the ISP_CTRL register.
10:8 DATSIZ = 0x0: cam_d is 8 bits but the 8 to 16-bit bridge is enabled in the ISP_CTRL register.
7 FLDMODE = 0 progressive
0 VDHDOUT = 0 input;
--------------------------------------
CCDC_SDR_ADDR is also configed.
--------------------------------
CCDC_HORZ_INFO:
30:16 SPH Start pixel horizontal: 0
14:0 NPH Number of pixels horizontal: 480 - 1;
---------------------------------
CCDC_VERT_LINES:
14:0 NLV Number of lines - vertical direction: 640 - 1
-----------------
enable isp and ccdc
i tried to config CCDC_VDINT register , buf if 30:16 VDINT0 != 0, There will not generate CCDC_VD0_IRQ;
-============================================
REGISTERS :
RegisterName:==ISP_SYSCONFIG 1292== // 1292 is the pagenum of the dm3730 Manual
PHY_ADDRY:0x480bc004 VALUE0x1001
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0001 11-8:0000 7-4:0000 3-0:0001
---------------------------------------
RegisterName:==ISP_SYSSTATUS 1293==
PHY_ADDRY:0x480bc008 VALUE0x1
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0001
---------------------------------------
RegisterName:==ISP_IRQ0ENABLE 1294==
PHY_ADDRY:0x480bc00c VALUE0xf33f7fff
31-28:0111 27-24:0011 23-20:0011 19-16:1111 15-12:0111 11-8:1111 7-4:1111 3-0:1111
---------------------------------------
RegisterName:==ISP_CTRL 1308==
PHY_ADDRY:0x480bc040 VALUE0x1da10c
31-28:0000 27-24:0000 23-20:0001 19-16:1101 15-12:1010 11-8:0001 7-4:0000 3-0:1100
---------------------------------------
RegisterName:==ISP_IRQ0STATUS 1297==
PHY_ADDRY:0x480bc010 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==TCTRL_CTRL==
PHY_ADDRY:0x480bc050 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==PERIPHERAL CONTROL REGISTER 1363==
PHY_ADDRY:0x480bc604 VALUE0x3
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0011
---------------------------------------
RegisterName:==CCDC_SYN_MODE 1364==
PHY_ADDRY:0x480bc608 VALUE0x31000
31-28:0000 27-24:0000 23-20:0000 19-16:0011 15-12:0001 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_PIX_LINES 1367==
PHY_ADDRY:0x480bc610 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_HORZ_INFO 1368==
PHY_ADDRY:0x480bc614 VALUE0x27f
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0010 7-4:0111 3-0:1111
---------------------------------------
RegisterName:==CCDC_VERT_START 1369==
PHY_ADDRY:0x480bc618 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_VERT_LINES 1370==
PHY_ADDRY:0x480bc61c VALUE0x1df
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0001 7-4:1101 3-0:1111
---------------------------------------
RegisterName:==CCDC_HSIZE_OFF 1371==
PHY_ADDRY:0x480bc624 VALUE0x500
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0101 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_SDOFST 1372==
PHY_ADDRY:0x480bc628 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_SDR_ADDR 1373==
PHY_ADDRY:0x480bc62c VALUE0x86900000
31-28:0000 27-24:0110 23-20:1001 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_COLPTN 1375==
PHY_ADDRY:0x480bc638 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_FPC 1378==
PHY_ADDRY:0x480bc640 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==VD INTERRUPT REGISTER 1380==
PHY_ADDRY:0x480bc648 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_REC656IF ==
PHY_ADDRY:0x480bc650 VALUE0x0
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_CFG 1382==
PHY_ADDRY:0x480bc654 VALUE0x8000
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:1000 11-8:0000 7-4:0000 3-0:0000
---------------------------------------
RegisterName:==CCDC_FMTCFG 1384==
PHY_ADDRY:0x480bc658 VALUE0x4000
31-28:0000 27-24:0000 23-20:0000 19-16:0000 15-12:0100 11-8:0000 7-4:0000 3-0:0000
Now, I read out the image buffer , the second line - 480th line is all 0xffff .
I'm so so sorry for my English language ability.