I want to recevie VGA UYVY data from sensor .
sensor --> CCDC----> memory
parallel 8 bits .
how to config the registers of ISP and CCDC ?
this is my configration:
ISP_SYSCONFIG:
MIDLE_MODE =No-standby:
AUTO_IDLE = 0x1: Automatic clock gating strategy
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ISP_CTRL:
ISPCTRL_CCDC_CLK_EN
ISPCTRL_CCDC_RAM_EN
ISPCTRL_RSZ_CLK_EN
SYNC_DETECT==0x2: VS falling edge
SHIFT = 0x3: Shift by 6 CAMEXT[13:6] - CAM [7:0]
|ISPCTRL_CCDC_FLUSH
|ISPCTRL_SBL_WR0_RAM_EN
|ISPCTRL_SBL_WR1_RAM_EN
|ISPCTRL_SBL_RD_RAM_EN
PAR_BRIDGE = 0x3: The bridge is enabled. The first byte is written toCAM.DATA[15:8], the second byte is written toCAM.DATA[7:0]
PAR_SER_CLK_SEL= 0x0: Selects the 12-bit parallel interface as the input tothe CCDC module.
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IRQ0ENABLE :
IRQ0STATUS_HS_VS_IRQ |
IRQ0STATUS_RSZ_DONE_IRQ |
IRQ0STATUS_CCDC_VD0_IRQ |
IRQ0STATUS_CCDC_VD1_IRQ;
----------------------------------
CCDC_CFG:
VDLC == 0x1: Not latched on VS
-------------------------------------------------------
CCDC_SYN_MODE
17 WEN ==1 Data write enable.
16 VDHDEN = 0x1: Enable;
13:12 INPMOD = 0x1: YCbCr data on 16 bits. It is required to enable the 8to 16-bit bridge in the ISP_CTRL register.
10:8 DATSIZ = 0x0: cam_d is 8 bits but the 8 to 16-bit bridge is enabled in the ISP_CTRL register.
7 FLDMODE = 0 progressive
0 VDHDOUT = 0 input;
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CCDC_SDR_ADDR is also configed.
--------------------------------
CCDC_HORZ_INFO:
30:16 SPH Start pixel horizontal: 0
14:0 NPH Number of pixels horizontal: 480 - 1;
---------------------------------
CCDC_VERT_LINES:
14:0 NLV Number of lines - vertical direction: 640 - 1
-----------------
enable isp and ccdc
i tried to config CCDC_VDINT register , buf if 30:16 VDINT0 != 0, There will not generate CCDC_VD0_IRQ;
please tell me where is wrong , or which register is not set .
thank you .
