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DM3730 Spread Spectrum Clocking

Other Parts Discussed in Thread: DM3730

I'm trying to enable SSC (Spread Spectrum Clocking) feature for DM3730 Processor to reduce the EMI from our LCD and camera modules. I write modulation frequency and DeltaMStep values ( 0xFECDC09 - for 1% variation; calculated as per the TRM) in CONTROL_PER_DPLL_SPREADING_FREQ and enbling it by writing 0x10 in the CONTROL_PER_DPLL_SPREADING register. When I probe the LCD PCLK I did see some spreading. But it is not consistant. When I entered the values today I didn't see any change. Please give me any suggestions.

Thanks in advance,

Prathap

  • Hi Prathap,

    Could you share what is the spreading range when you probed the LCD PCLK ?

    BR

    Tsvetolin Shulev

  • Hi Shulev,
     
    Actually I got my calculations wrong earlier. Now I got my calculations correct.
     
    We get more emissions from LCD cable, we decided to explore SSC feature. The Clock architecture diagram shows DPLL4 drives LCD,Camera, UART etc. Now when I enable SSC feature, our URAT baud rate gets affected and communication fails. 
    Is this expected? 
     
    For DPLL4 we use M=864, N=12, M4 = 30(for DSS to get 28.8MHz), M5=0x4 (for CAM to get 24MHz clock).
    for 0.3% deviation with 10db PPR my calculated value is = 16EEFE7
    for 0.4% deviation with 10db PPR my calculated value is = ​28C4FA5
     
  • Hi Prathap,

    Now your calculations seems correct and these are the expected values.

    BR

    Tsvetolin Shulev

  • Hi Shulev,
     
    While enabling the spreading for DPLL4, does the UART2 which is also derived from PLL4,  also gets spread?
    When enabling SSC, we are having communication failure on UART bus.
    The device connected to UART2 passes with 0.1% deviation, but fails when i increase the deviation to > 0.2%.
     
    Is there any way I can ensure that SSC is not set for the UART module and only for the LCD module?
     
    Thanks,
    Prathap