To make the code in 1. (as below in spruf98d.pdf) work, what base addresses and offset for CM_CLKSEL3_EMU, declared where, are needed?The steps 1.) and 2.) outlined below are coded by me (Ion Beza) in omap2_mcspi.c, it was not pre-existing code in omap2_mcspi.c. Support for base address and offset OMAP2_MCSPI_CHCONF0 exists, maybe in u-boot whose source code Gumstix has and we don't; support for my desired base address and offset CM_CLKSEL3_EMU does not exist, and I would like it to similar to (in u-boot?) OMAP2_MCSPI_CHCONF0 and chconf0.So,Question:_________The code existing in omap2_mcspi.c for step 1.://#define CM_CLKSEL3_EMU 0x54#define CM_CLKSEL3_EMU 0x3154 l = mcspi_read_reg(master, CM_CLKSEL3_EMU); /* Set bit 12 in CM_CLKSEL3_EMU to 1. */// MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_TRM_RX_ONLY, 1); /* Set bit 9 in CM_CLKSEL3_EMU to 1. */ l &= (0xFFFFFDFF); l |= (0x200); mcspi_write_reg(master, CM_CLKSEL3_EMU, l);doesn't work, maybe due to a base address and offset CM_CLKSEL3_EMU not declared anywhere when doing a search on the computer, but declared maybe in u-boot whose source code is written by Gumstix and we don't have. (we found though source code for Das Boot, a code similar to u-boot, and we are searching there)The code in omap2_mcspi.c for 2.): l = mcspi_read_reg(master, OMAP2_MCSPI_CHCONF0);// MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 1); l &= (0xDFFFFFC3); l |= (0x8); mcspi_write_reg(master, OMAP2_MCSPI_CHCONF0, l);or a variant of it: l = cs->chconf0; l &= (0xDFFFFFC3); l |= (0x8); cs->chconf0 = l;does work probably due to base addresses and offset declared in u-boot.To make the code in 1.) work, what base addresses and offset for CM_CLKSEL3_EMU, declared where, are needed?The Background___________My PALO43 (with OMAP3530 in it) is to connect to a ADS1278 via an SPI bus running from Controller 1 Chip Select 0 of the OMAP3530. The Operating System is Gumstix's Angstrom Linux 2.6.32-r51.The SPI clock is observed free-running on pin 171.clk1 of PALO43 at 48 Mhz when the code below in omap2_mcspi.c is disabled: ret = omap2_mcspi_setup_transfer(spi, NULL); omap2_mcspi_disable_clocks(mcspi);For the SPI transaction to happen, OMAP has to lower the SPI clock to 27 Mhz or less, like the ADS 1278 clock. Theoretically when the code is enabled back, the SPI clock runs at 48 Mhz, sets the SPI settings in the function omap2_mcspi_setup_transfer, at Chip Enable low in general or here at /DRDY the SPI clock starts running at the new settings set in omap2_mcspi_setup_transfer, and the SPI transaction happens.The problem is that the OMAP3530 doesn't lower the SPI clock from 48 Mhz to 27 Mhz or less.To lower the SPI clock rate the TI document, spruf98d.pdf, gives 2 steps:1.) write M with a decimal value different than 0 or 1 in bits 8 to 18 in register CM_CLKSEL3_EMU in order to enable variable clock (per spruf98d.pdf pages 298 and 533); (this makes DPLL4_FCLK in page 298 which becomes mcspi->fck of 48 Mhz in the code not bypass the DPLL4 divisor anymore, but allows the divisor to produce the programmable clock L4_ICLK or mcspi->ick in the code; the flexible clock L4_ICLK in the doc or mcspi->mcspi->ick in the code goes on SPI bus)2.) set the divider of the 48 Mhz clock to 4 for example, by setting bit 3 (4th. bit) to 1 in register MCSPI_CH0CONF (in doc) or OMAP2_MCSPICHCONF0 (in code) in order to get SPI clock at 12 Mbps = 12 MHz (for example) (per spruf98d.pdf pages 2811 and 2882).
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