dpll3_m2_clk rate change failed: -22

shital gandhi1

Prodigy 140 points

Other Parts Discussed in Thread: OMAP3503

Hi.

I am using linux 2.6.32 kernel on omap3503 processor, which boots up successfully but at boot time it gives me error,

"dpll3_m2_clk rate change failed: -22" in log messages.

This error comes from arch/arm/mach-omap2/io.c file when SDRC clock rate is not able to set.

Here is the code of io.c file.

static int __init _omap2_init_reprogram_sdrc(void)
{
	struct clk *dpll3_m2_ck;
	int v = -EINVAL;
	long rate;

	if (!cpu_is_omap34xx())
		return 0;

	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	if (!dpll3_m2_ck)
		return -EINVAL;

	rate = clk_get_rate(dpll3_m2_ck);
	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	v = clk_set_rate(dpll3_m2_ck, rate);
	if (v)
		pr_err("dpll3_m2_clk rate change failed: %d\n", v);

	clk_put(dpll3_m2_ck);

	return v;
}


And log messages are as under,

Clocking rate (Crystal/Core/MPU): 26.0/266/600 MHz
Reprogramming SDRC clock
dpll3_m2_clk rate change failed: -22
GPMC revision 5.0
IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts

Help me to resolve this issue.

Reply is awaited

Thanks

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Moving your post to right forum to be better answered.

Thanks & regards,
Sivaraj K

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Hi Shital,

According to the posted log I can conclude that the clk_set_rate function fails to set desired 'rate' but in the log I could not see what is the value of the 'rate' variable and I'm wondered why the row 'Reprogramming SDRC clock' is not completed.
Could you try to print the value of the 'rate' variable? Also after booting could you check the current cpu freq and all available frequencies by the commands:
# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies

BR
Tsvetolin Shulev

0 Cvetolin Shulev-XID over 8 years ago in reply to Cvetolin Shulev-XID

TI__Guru 65405 points

Moving the thread to DM37x forum because OMAP35x Forum is set for read only (archived) and the customers cannot reply as the thread is posted in a read only Forum.

BR
Tsvetolin Shulev

0 Dmitry Bodnya over 8 years ago in reply to Cvetolin Shulev-XID

Expert 1140 points

Hi Cvetolin!

I have the same problem during boot.

Clocking rate (Crystal/Core/MPU): 26.0/266/600 MHz
Reprogramming SDRC clock to 266000000 Hz
dpll3_m2_clk rate change failed: -22

# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
1000000

# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequ
encies
300000 600000 800000 1000000

MPU clk is set(to 1GHz) in u-boot. I don't know why kernel prints 600 MHz. And if I am choosing mpurate=500 boot param it prints that reprogramming is successful but debugfs still shows arm_fck 1 000 000 000...

0 shital gandhi1 over 8 years ago in reply to Dmitry Bodnya

Prodigy 140 points

Hi Cvetolin,

I have fixed this issue, it is occurring because SDRC clock which you are setting, kernel does not have that structure in DDR register setting file.
In my case I have to add structure in "arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h"

I hope this will solve your problem.

Thanks,
Shital

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dpll3_m2_clk rate change failed: -22