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3530 mCSPI
Related Posts

  • Forum Post: RE: About McBsp or MCspi for OMAP3530

    dan li1
    hi Bhimesh， Have you found a McBSP or McSPI C code for any A/D converter that works from DSP side of omap 3530 ? I am in the same situation as you were. email me at xiaoruichan@126.com thanks a lot linda
    on Jun 13, 2012

  • Forum Post: Problem on 5-megapixel camera

    yuanjun ren
    Hi,all platform: OMAP3530 os:wince 6.0 BSP:BSP BSP_WINCE_ARM_A8 1.01.00.03 camere: OV5642 In my camera driver, When I use 2 - megapixel to capture image , the ov5642 is ok, but I change the pixel format as 5- megapixel ,It does not work . what is the reason?
    on Jun 20, 2012

  • Forum Post: RE: BB-xM + DSPLink + C6Accel + OpenCV

    Huangbao Liu
    Sir, Recently, I am focusing on using C6Accel,but I don't know how to builing it .Can you tell me the steps on how to build C6Accel and use it in detail .I also reqest you tell me the depencies of C6Accel. I do hope you can reply me as soon as possible ! Thank you very much ! Best wishes for...
    on Jul 18, 2012

  • Forum Post: DPLLs in bypass mode during suspend state

    ajit basarur
    Hi, We have a custom DM37x based board. In this custom board we have implemented suspend state for the BSP to achieve the lowest possible power state. All the peripherals are configured to operate in Auto IDLE mode and SDRAM controller is configured to enter Self Refresh mode. In addition we want...
    on Jul 20, 2012

  • Forum Post: RE: what is balanced/unbalanced clock?

    ajit basarur
    Dear All, I have a related query on 48M_FCLK. We have a system with support for suspned/resume. During suspend state, we put CORE clock to 48 MHz and during resume we move back the CORE clock to 200 MHz. After resume we observe that USB HOST domain (EHCI controller) and SPI2 are not functioning in...
    on Sep 6, 2012

  • Forum Post: DM37x DSP DPLL2 Lock Issue

    ajit basarur
    Dear All, I am facing a peculiar problem with DSP DPLL2 lock mechanism. During normal operation mode, I am able to put DPLL2 in bypass mode, set M2, M and N values and then lock it. However If DPLL2 is enabled for AutoIdle mode (Set Bit[2-0] to value 0x1 in register CM_AUTOIDLE_PLL_IVA2) then DSP...
    on Aug 22, 2012

  • Forum Post: DM3730 DSP Acceleration issue

    Srinivas Marakala1
    We are trying to enable DSP acceleration on DM3730 based Android custom platform (using Variscite VAR-OM37X SOM). We tried on DSP Acceleration on Mistral EVM platform and it works. We are using the same file system on our platform and it fails with following error. I/omx-dsp ( 1145): 1292529286 [INTERFACE...
    on Dec 5, 2012

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