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  • Forum Post: Engine open succeed but VIDENC_cretate() return NULL

    Wen Liu44416
    Hello, I used codec engine wizard to build my server.The codec are from cs1omap3530_1_00_01. The engine contains audio_copy and H264 algorithm. I can run audio_copy instance but when invoke VIDENC_create() the function returns NULL. I can compile the application and the server. But when I run the...
    on Oct 12, 2010

  • Forum Post: OProfile with OMAP3530

    Cruise Huang
    Hi Anybody tried OProfile on OMAP3530 ? My linux kernel is 2.6.29-rc3-omap, configured with OProfile enabled and build oprofile-0.9.6 . then opcontrol --init opcontrol --setup -i mybin --event=CPU_CYCLES:10000::0:1 opcontrol --start ...run my bin opcontrol -dump opreport -l...
    on Aug 8, 2010

  • Forum Post: Omap processor on Beagleboard-xM not booting kernel stops after booting kernel

    Marc Ghiron
    I am trying to boot up the demo version of angstrom on my beagleboard-xm I start by connecting the beagle board to my computer(running latest version of ubuntu) I have used both minicom and a program called serial port terminal to connect to the board. The port settings are set to tty/USB0 for...
    on Feb 4, 2011

  • Forum Post: RE: OMAP3530+OV3640 driver for wince6.0

    xiping xiao
    BOOL CIspCtrl::CCDCConfigSize(ULONG width,ULONG height) { ISP_OutReg32(&m_pCCDCRegs->CCDC_HSIZE_OFF, (width*2)&ISP_32B_BOUNDARY_OFFSET); ISP_OutReg32(&m_pCCDCRegs->CCDC_SDOFST, 0x0); /* Set the horizontal info */ ISP_OutReg32(&m_pCCDCRegs->CCDC_HORZ_INFO, (0<< ISPCCDC_HORZ_INFO_SPH_SHIFT...
    on May 25, 2012

  • Forum Post: RE: OMAP3530+OV3640 driver for wince6.0

    xiping xiao
    +CCDCInit,width = 640, height=480 +CCDCInitCFG -CCDCInitCFG +CCDCInitSYNC +ISPConfigSize, width =640 ,height =480 -CCDCInit ISP_SYSCONFIG =0x1001 ISP_CTRL =0x98140 TCTRL_CTRL =0x9 ISP_IRQ0ENABLE =0x0 CCDC_SYN_MODE =0x32700 CCDC_PCR =0x0 CCDC_HORZ_INFO =0x27f CCDC_VERT_START =0x0 CCDC_VERT_LINES =0x1df...
    on May 25, 2012

  • Forum Post: RE: OMAP3530+OV3640 driver for wince6.0

    xiping xiao
    Hi SathyaKumar , Thanks for your advice, I checked all registers and found that the ISP_CTRL.SHIFT should be set to shift 4bits, rather than 2bits. After changing, the camera image became stable without rolling or blurred screen. But it still fills only a quarter of the top screen. the image was...
    on Jun 1, 2012

  • Forum Post: OMAP3530+OV3640 driver for wince6.0

    xiping xiao
    hi I'm dealing with OV3640 driver on WINCE6.0 platform, the OV3640 module works well now, the out data format is YUV422. I set OMAP3530's ISP&CCDC register in the driver ,but i can only get a blurred screen,with which fills only a quarter of the top csreen. I do not know why .
    on May 25, 2012

  • Forum Post: DM37xx EHCI and OTG suspend state power consumption

    ajit basarur
    Hi, We have a custom DM37x based board with two USB interfaces MUSB OTG and EHCI. We have implemented suspend state within the BSP and in that state following is implementated for the two USB interfaces. EHCI: EHCI controller of DM37x is connected to external PHY. Suspend state is entered by enabling...
    on Jul 12, 2012

  • Forum Post: DPLLs in bypass mode during suspend state

    ajit basarur
    Hi, We have a custom DM37x based board. In this custom board we have implemented suspend state for the BSP to achieve the lowest possible power state. All the peripherals are configured to operate in Auto IDLE mode and SDRAM controller is configured to enter Self Refresh mode. In addition we want...
    on Jul 20, 2012

  • Forum Post: RE: what is balanced/unbalanced clock?

    ajit basarur
    Dear All, I have a related query on 48M_FCLK. We have a system with support for suspned/resume. During suspend state, we put CORE clock to 48 MHz and during resume we move back the CORE clock to 200 MHz. After resume we observe that USB HOST domain (EHCI controller) and SPI2 are not functioning in...
    on Sep 6, 2012

  • Forum Post: DM37x DSP DPLL2 Lock Issue

    ajit basarur
    Dear All, I am facing a peculiar problem with DSP DPLL2 lock mechanism. During normal operation mode, I am able to put DPLL2 in bypass mode, set M2, M and N values and then lock it. However If DPLL2 is enabled for AutoIdle mode (Set Bit[2-0] to value 0x1 in register CM_AUTOIDLE_PLL_IVA2) then DSP...
    on Aug 22, 2012

  • Forum Post: DM3730 DSP Acceleration issue

    Srinivas Marakala1
    We are trying to enable DSP acceleration on DM3730 based Android custom platform (using Variscite VAR-OM37X SOM). We tried on DSP Acceleration on Mistral EVM platform and it works. We are using the same file system on our platform and it fails with following error. I/omx-dsp ( 1145): 1292529286 [INTERFACE...
    on Dec 5, 2012

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