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Related Posts

  • Forum Post: RE: [MIDAS 2.0]: MIDAS build failure

    hyungchul won
    Thank you for your advice. I try your advice as blow. 1. TI dvsdk and TI midas should be under same parent folder. host $ mv /home/won/dvsdk/dvsdk_3_00_02_44 /home/won/ So, TI dvsdk move. /home/won/dvdsk_3_00_02_44 /home/won/midas 2. I try step2 and modify dvsdk_3_00_02_44/Rules.make...
    on Apr 23, 2012

  • Forum Post: OMAP3530+OV3640 driver for wince6.0

    xiping xiao
    hi I'm dealing with OV3640 driver on WINCE6.0 platform, the OV3640 module works well now, the out data format is YUV422. I set OMAP3530's ISP&CCDC register in the driver ,but i can only get a blurred screen,with which fills only a quarter of the top csreen. I do not know why .
    on May 25, 2012

  • Forum Post: Problem of camera driver in WINCE DM37X version

    yuanjun ren
    Hi,all I'm dealing with OV5640 driver on WINCE6.0 platform, the out data format is YUV422. the OV5640 module works well for 2MP-Still, but I change to 5MP-Still, It is not normal. The BSP I used is BSP_WINCE_ARM_A8 1.01.00.03.
    on Jun 16, 2012

  • Forum Post: Automation of FLASH v1.6.0.0 utility for programming the NAND

    Mahesh Hooli
    Hello All, We are using FLASH v1.6.0.0 utility for programming the NAND (for flashing the WinCE image onto NAND). We are flashing it using through USB. Is there any options to make run these FLASH v1.6.0.0 utility commands using DOS prompt? In production, we would like to automate the flashing...
    on Jul 16, 2012

  • Forum Post: DPLLs in bypass mode during suspend state

    ajit basarur
    Hi, We have a custom DM37x based board. In this custom board we have implemented suspend state for the BSP to achieve the lowest possible power state. All the peripherals are configured to operate in Auto IDLE mode and SDRAM controller is configured to enter Self Refresh mode. In addition we want...
    on Jul 20, 2012

  • Forum Post: RE: what is balanced/unbalanced clock?

    ajit basarur
    Dear All, I have a related query on 48M_FCLK. We have a system with support for suspned/resume. During suspend state, we put CORE clock to 48 MHz and during resume we move back the CORE clock to 200 MHz. After resume we observe that USB HOST domain (EHCI controller) and SPI2 are not functioning in...
    on Sep 6, 2012

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