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Digital Signal Processors (DSP)

Welcome to the Digital Signal Processors (DSP) Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

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.bin loading error
  • .5mm
  • .args Beagle DM3730 c6runapp
  • /ultrasound/ultrasound': No such file or directory
  • [hw]
  • 0x48)
  • 1.8V 3.3V 5V SPI GPIO
  • 1.8V GPIO
  • 15 BSP LCD Backlight
  • 16550
  • 16-bit camera
  • 2.6.22.18
  • 2.6.29-rc3-omap1
  • 2.6.32
  • 2.6.37
  • 26.4MHz oscillator
  • 3.3V
  • 32kHz clock
  • 3517 barebox
  • 3530
  • 3530 mCSPI
  • 3530 oprofile
  • 3530 clock
  • nor flash
  • OMPA35x
Related Posts
  • Forum Post: Programming to an address on the NOR flash for OMAP3517

    N53196 N53196
    Hi, I am trying to load a bsp to the NOR flash for OMAP3517 at a specified address. Here is my configuration: 1. Custom board with OMAP3517 Cortex A8 core 2. Signum JTAG 3. CCS 4.1.2.00027 I have done the following so far: 1. Selected the target as OMAP 3515 since OMAP 3517 was not...
    on Jul 9, 2010
  • Forum Post: Automation of FLASH v1.6.0.0 utility for programming the NAND

    Mahesh Hooli Mahesh Hooli
    Hello All, We are using FLASH v1.6.0.0 utility for programming the NAND (for flashing the WinCE image onto NAND). We are flashing it using through USB. Is there any options to make run these FLASH v1.6.0.0 utility commands using DOS prompt? In production, we would like to automate the flashing...
    on Jul 16, 2012
  • Forum Post: DPLLs in bypass mode during suspend state

    ajit basarur ajit basarur
    Hi, We have a custom DM37x based board. In this custom board we have implemented suspend state for the BSP to achieve the lowest possible power state. All the peripherals are configured to operate in Auto IDLE mode and SDRAM controller is configured to enter Self Refresh mode. In addition we want...
    on Jul 20, 2012
  • Forum Post: RE: what is balanced/unbalanced clock?

    ajit basarur ajit basarur
    Dear All, I have a related query on 48M_FCLK. We have a system with support for suspned/resume. During suspend state, we put CORE clock to 48 MHz and during resume we move back the CORE clock to 200 MHz. After resume we observe that USB HOST domain (EHCI controller) and SPI2 are not functioning in...
    on Sep 6, 2012
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