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c6472
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  • Forum Post: Six-core TMS320C6472, industry’s best power efficiency & EVM giveaway

    HulaGirl
    New six-core TMS320C6472 offers industry’s best power efficiency for performance-hungry applications The devices are available with six integrated cores in a single chip, either running at 500, 625 or 700 MHz. The C6472 is fully optimized for applications where performance per watt is...
    on Nov 3, 2009

  • Forum Post: Configuring Cache in DSP BIOS v6

    Tom Goossens
    Hello all, Did anybody find a good example / tutorial for how to configure the cache in a DSP BIOS version 6 project? Of course I did find the cache module ( ti.sysbios.hal.Cache ). But I'm a bit at loss in how to use it. I would like to enable the L1P, L1D, LL2 and SL2 caches and the MAR on...
    on Nov 4, 2009

  • Forum Post: SRIO boot problem

    sungyi chen
    To whom might concern, I was trying to boot TCI6486 by SRIO boot mode. I could load DSP image by SRIO and boot CPU1~CPU5 successfully. I set a boot.asm to jump to _c_int00 at address 0x10200000 and set boot_start address and BOOT_COMPLETE_STAT. Set (boot_start address) 0x10200000 into (DSP_BOOT_ADDR1...
    on Nov 10, 2009

  • Forum Post: TCI6486 power consumption

    sungyi chen
    To whom might concern, When I tried to run while loop, TCI6486 power consumption was increasing and higher than any tasking like: SRIO, EMAC or EDMA. Does anyone can tell me why? Sincerely, SUNGYI CHEN
    on Dec 11, 2009

  • Forum Post: Some question about EVM6472

    sergey manuhin
    Good morning I have some question about EVM6472. 1)I want to work with this processor by the CCS 3.3 but I haven't got any drivers for this processor. Can I work with this board by CCS 3.3 or should I do it by CCS 4? 2) I have found LLD and MQT libraries for 6474 but they can't support my processor...
    on Jan 15, 2010

  • Forum Post: C6472 semaphore address

    Peter Robertson
    The document SPRUG14 describes the C64 semaphores and gives offsets for the various registers involved, but I have been unable to find any document that gives the base address to which these offsets apply. Where can I find this information for the C6472?
    on Jan 19, 2010

  • Forum Post: Adding external SRAM and interfacing to more than 512MB of DDR2 to c6472

    SNBANIK
    Hello, 1. Is there a way to interface c6472 to more than 512MB of DDR2 memor? 2. Is there any to interface c6472 to external SRAM? Thanks, Somnath Banik
    on Jan 27, 2010

  • Forum Post: Ethernet bootloading to a core other than core0

    Arya Stark42598
    I've been trying to work with the EMAC bootloader on the C6472 multicore DSP. What I have is a very simple code that writes to the DDR. It writes a constant, and then the number of the core running. I have managed to make this program run on core 0 (I just load the program, and then check the...
    on Feb 14, 2010

  • Forum Post: Sourcing Clock Inputs to the C6472

    Jon Jensen
    To save on the number of oscillators, can all three clocks for the C6472 come from the same clock source? The datasheet specifies a range for each PLL input, and 25MHz falls in this range for all three. I know this will limit the DDR2 clock to 500MHz, but this is not an issue for our application. I am...
    on Mar 22, 2010

  • Forum Post: RGMII Termination

    Jon Jensen
    Looking through the data sheets and app notes for the C6472, I do not see any mention of whether or not there is internal termination for RGMII. Most PHYs have both input parallel and output series termination. I have seen processors to have one or the other, none, or both. What does the C6472 have?...
    on Mar 31, 2010

  • Forum Post: Unused Pins on the DDR2 Interface

    Jon Jensen
    The C6472 datasheet gives the option of using 1 x16 DDR2 device. The appnote spraat7d does not give any guidance to using just one device. My main concern is how should we connect the unused pins? These pins would include the higher 2 bytes for the chip select, mask, data strobe, data strobe gate...
    on Apr 13, 2010

  • Forum Post: Working with the TMDXEVM6472

    Arya Stark42598
    I've been trying to run a simple program on the TMDXEVM6472. The program is the EMAC loopback example given with CCS4 along with the board. I have two problems: 1. The program is little endian. On the EVM, there's a switch that should change between big and little endian. Changing this...
    on Apr 27, 2010

  • Forum Post: C6472 CSL

    Arya Stark42598
    I've recently started working with the EVM6472. I have installed the latest version of CCS4, and downloaded the CSL for C6472, but when I try to compile code, I get unresolved external symbols for functions like CSL_intcGlobalEnable or CSL_tmrOpen. Am I missing some .lib file? Am I using the...
    on Apr 28, 2010

  • Forum Post: Task_Yield in BIOS6

    SNBANIK
    Here are my questions related to Task_Yield in BIOS6-- 1. Does Task_Yield result in the currently active task temporarily yielding the CPU? In other words, does the task come back and resume what it was doing? 2. My need is for the task to abandon what it was doing and go back to Pend call. Will...
    on May 12, 2010

  • Forum Post: DDR2 Maximum Speed

    Arya Stark42598
    Hello, I'm trying to figure out how fast I can write/read from the DDR2 with C6472 (using one core only, for now). My program write in blocks using memset. I've tried many sizes, but starting from 1024 bytes there doesn't seem to be much difference. To get maximal speed, I use...
    on May 16, 2010

  • Forum Post: Can I connect two TMS320C6472 via RGMII?

    haopeng han
    Hi,all I am now designing a board with 4 TMS320C6472. I was wondering can two DSPs connect via EMAC directly? Luckly, I find a post by jean-philippea who wants to connect C6472 to a FPGA via EMAC.( http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/t/31757.aspx ) And RandyP points out it's...
    on Jun 2, 2010

  • Forum Post: Code Generation in Linux for C6472 EVM kit

    Pranav Desai51514
    Hello All, I planning to generate code in Linux environment for C6472 EVM using the TI Linux Code generation tools found on the TI website. I am planning to use Virtual Box with Ubuntu on a Windows XP host. I am planning to run the TI test examples first. Please let me know if you guys foresee...
    on Jun 9, 2010

  • Forum Post: C6472 HPI Bootloader Question

    Ray Cariseo
    We are using the TMS320C6472 6-core DSP and will be loading code using the HPI Interface. It appears that some of the documentation for using this interface for the C6472 conflicts each other. The Bootloader User’s Guide (SPRUEC6D), under the C6472 HPI Boot section (4.3.1), states “...
    on Jul 9, 2010

  • Forum Post: Re: C6472 Utopia2

    Charles Gray
    Just thought I would refresh this forum question... Has anyone used the Utopia peripheral with this DSP? Regards, Charles
    on Jul 14, 2010

  • Forum Post: Questions regard to C6472 Power Sleep/Wake Controller

    Binh Vu
    I have some questions regarding dynamic power managment on C6472 When a certain core of C6472 is in power sleep mode, is the core completely turned off or the core is just in sleep mode with low CPU usages? If the cores (especially all cores) are turned OFF or in sleep mode, I belive it would...
    on Jul 22, 2010

  • Forum Post: OK to program 6472 PLL1 using HPI ?

    Greg Reuter
    Hi, SPRS612D says HPI can configure PLL controller registers, but SPRU806A says HPI should not access them. TMS320C6472 data sheet SPRS612D section 2.4.1 (Host boot): “Initial HPI accesses can configure PLL1 for full-speed operation to make HPI accesses shorter. TMS320C6472 PLL...
    on Jul 26, 2010

  • Forum Post: Configuring C6472 PLL registers with HPI

    Greg Reuter
    Should I configure C6472 PLL1 registers with HPI ? SPRS612D says YES (section 2.4.1, page 17, paragraph 1, lines 7-8). SPRU806A says NO (section 3.1, page 9, paragraph 2)
    on Jul 30, 2010

  • Forum Post: Can't access C6472 TSIP registers

    Greg Reuter
    All TSIP register locations appear to read 0 for both HPI and JTAG. For example, the TSIP PID (address 0x02500000) reads 0x00000000 (0x00600101 expected). If it matters, the PLL1 PID and HPI PID read as expected, but the SRIO PID (address 0x02D00000) reads 0.
    on Jul 30, 2010

  • Forum Post: C6472 The IPCGR and IPCAR

    yang zhang53096
    The IPCGRn (IPCGR0 thru IPCGR5) and IPCARn (IPCAR0 thru IPCAR5) registers facilitate inter-DSP interrupts. This can be utilized by external hosts or C64x+ megamodules to generate interrupts to other DSPs. A write of 1 to the IPCG field of IPCGRn register generates an interrupt pulse to C64x+ Megamodulen...
    on Aug 3, 2010

  • Forum Post: Re: Simultaneous access of shared memory in 6472

    one and zero
    Hi AC, the answer is yes. The Shared L2 is: • Optimized for prefetchable memory reads – Speculative prefetching – 0 wait state prefetch hits at max CPU clock = 500 MHz – Selectable prefetchable and non-prefetchable memory region • LRU-based arbitration per bank ARB...
    on Sep 23, 2010
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