We have a doubt about burst tranfers.
When a burst tranfer occours and the channel doesn't have permission to write, what happen with the elements that are coming into the FIFO if the frame has more than nine elements? Are these elements lost or is the channel initialized again? Is there any interruption to advise the CPU that a transfer failed?
Assuming the standard C64x+ EDMA3 (likely applies to other TI DMAs as well), a bursting transfer will stall if an endpoint is not available immediately for some reason, so the transfer just slows down but you should not be losing data in the DMA itself thus there is no interrupt. You would only lose data if a real time deadline is broken with something you are servicng with the DMA (for example a video port is not serviced in time).
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.